公开(公告)号：US20230154894A1

公开(公告)日：2023-05-18

申请号：US17862496

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jegwan HWANG ,  Jihyung KIM ,  Jeong Hoon AHN ,  Jaehee OH ,  Shaofeng DING ,  Won Ji PARK ,  WooSeong JANG ,  Seokjun HONG

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L24/05 ,  H01L24/13 ,  H01L25/50 ,  H01L23/5286 ,  H01L2224/05567 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L24/73 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L24/06 ,  H01L2224/06181 ,  H01L24/17 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2224/16225 ,  H01L2225/06544 ,  H01L25/18

Abstract: A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.