公开(公告)号：US09496277B2

公开(公告)日：2016-11-15

申请号：US14723644

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L27/105 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

公开(公告)号：US09276058B2

公开(公告)日：2016-03-01

申请号：US14732260

申请日：2015-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho Lee ,  Jin Choi ,  Yong-Ho Yoo ,  Jong-Hyuk Kang ,  Hyun-Joo Cha ,  Hee-Dong Park ,  Tae-Jung Park

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/60

Abstract: A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction.

Abstract translation: 半导体器件包括在基片上的多个下电极，其中每个下电极从衬底沿高度方向延伸并且包括侧壁，下电极在第一方向和第二方向彼此间隔开， 与下电极的侧壁接触的多个第一支撑层图案，第一支撑层图案沿着第一方向在第二方向上相邻的下电极之间延伸;多个第二支撑层图案，其与下部电极的侧壁接触; 电极，所述第二支撑层图案沿着所述第二方向在与所述第一方向相邻的所述下电极中的所述第二方向延伸，所述多个第二支撑层图案在所述高度方向上与所述多个第一支撑层图案间隔开。

公开(公告)号：US20130065381A1

公开(公告)日：2013-03-14

申请号：US13673396

申请日：2012-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong- Wook Lee ,  Jong-Hyuk Kang

IPC: H01L21/20

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

公开(公告)号：US20140080273A1

公开(公告)日：2014-03-20

申请号：US14083971

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L27/105 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract translation: 在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上 设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。 晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

公开(公告)号：US20130134501A1

公开(公告)日：2013-05-30

申请号：US13750066

申请日：2013-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7841

Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

Abstract translation: 在垂直型半导体器件中，其制造方法及其操作方法，垂直型半导体器件包括：具有设置在基板上的柱状的单晶半导体图案， 单晶半导体图案，并且具有比单晶半导体图案的上表面低的上表面，形成在栅极的上表面上的掩模图案，所述掩模图案具有与单个半导体图案的上表面共面的上表面 晶体半导体图案，在单晶半导体图案下的衬底中的第一杂质区域和在单晶半导体图案的上表面下方的第二杂质区域。 形成在单晶半导体图案中的垂直型立柱晶体可以提供优异的电性能。 在第二杂质区域中的单晶半导体图案的上表面上没有设置掩模图案，从而减少处理的失败。

公开(公告)号：US20170012054A1

公开(公告)日：2017-01-12

申请号：US15275972

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/792 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/45 ,  H01L21/285

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract translation: 在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上 设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。 晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

公开(公告)号：US09029939B2

公开(公告)日：2015-05-12

申请号：US13750066

申请日：2013-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7841

Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

Abstract translation: 在垂直型半导体器件中，其制造方法及其操作方法，垂直型半导体器件包括：具有设置在基板上的柱状的单晶半导体图案， 单晶半导体图案，并且具有比单晶半导体图案的上表面低的上表面，形成在栅极的上表面上的掩模图案，所述掩模图案具有与单个半导体图案的上表面共面的上表面 晶体半导体图案，在单晶半导体图案下的衬底中的第一杂质区域和在单晶半导体图案的上表面下方的第二杂质区域。 形成在单晶半导体图案中的垂直型立柱晶体可以提供优异的电性能。 在第二杂质区域中的单晶半导体图案的上表面上没有设置掩模图案，从而减少处理的失败。

公开(公告)号：US20190035809A1

公开(公告)日：2019-01-31

申请号：US16139285

申请日：2018-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L27/11582 ,  H01L29/792 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/423 ,  H01L27/11578 ,  H01L27/11568 ,  H01L27/105 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/285 ,  H01L21/28 ,  H01L27/1158

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

公开(公告)号：US10109642B2

公开(公告)日：2018-10-23

申请号：US15275972

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/792 ,  H01L27/105 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3213 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/45 ,  H01L27/1158

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

公开(公告)号：US09070581B2

公开(公告)日：2015-06-30

申请号：US14083971

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L21/336 ,  H01L27/105 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract translation: 在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上 设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。 晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。