公开(公告)号：US20180158809A1

公开(公告)日：2018-06-07

申请号：US15693707

申请日：2017-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Wan Kim ,  Sung-Chul Park ,  Won-Il Bae

IPC: H01L25/18 ,  H01L25/065 ,  G11C7/10

CPC classification number: H01L25/18 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1006 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49052 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor memory device includes a memory structure including a first integrated circuit chip and a plurality of second integrated circuit chips stacked on each other, the first integrated circuit chip is interposed between a pair of the plurality of second integrated circuit chips, an interface unit disposed on the first integrated circuit chip, the memory structure is connected to a third circuit through the interface unit, and the interface unit transfers operation signals to the first integrated circuit chip and the plurality of second integrated circuit chips, at least one inter-chip interconnector connected with the interface unit and the first integrated circuit chip and the plurality of second integrated circuit chips, and an external interconnector connected with the interface unit and the third circuit.

公开(公告)号：US10229900B2

公开(公告)日：2019-03-12

申请号：US15693707

申请日：2017-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Wan Kim ,  Sung-Chul Park ,  Won-Il Bae

IPC: G11C5/02 ,  H01L25/18 ,  H01L25/065 ,  G11C7/10 ,  G11C5/04 ,  G11C5/06

Abstract: A semiconductor memory device includes a memory structure including a first integrated circuit chip and a plurality of second integrated circuit chips stacked on each other, the first integrated circuit chip is interposed between a pair of the plurality of second integrated circuit chips, an interface unit disposed on the first integrated circuit chip, the memory structure is connected to a third circuit through the interface unit, and the interface unit transfers operation signals to the first integrated circuit chip and the plurality of second integrated circuit chips, at least one inter-chip interconnector connected with the interface unit and the first integrated circuit chip and the plurality of second integrated circuit chips, and an external interconnector connected with the interface unit and the third circuit.