公开(公告)号：US11417664B2

公开(公告)日：2022-08-16

申请号：US17034652

申请日：2020-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongin Kang

IPC: H01L27/108 ,  G11C5/06

Abstract: A semiconductor device includes a substrate including a first region having a first trench and a second region having a second trench. A first buried insulation layer pattern is disposed in the first trench. The second trench includes the first buried insulation layer pattern, a second buried insulation layer pattern, and a third buried insulation layer pattern sequentially stacked therein. A first buffer insulation layer is disposed on the substrate in the first and second regions and has a flat upper surface. A second buffer insulation layer is disposed on the first buffer insulation layer. A bit line structure is disposed on the first and second regions. A first portion of the bit line structure is disposed on the second buffer insulation layer and has a flat lower surface. A second portion of the bit line structure directly contacts a surface of the substrate in the first region.

公开(公告)号：US20230411157A1

公开(公告)日：2023-12-21

申请号：US18136407

申请日：2023-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungkyo Lee ,  Jongin Kang ,  Gyeyoung Kim ,  Youngwoo Kim ,  Yonghan Park ,  Woojin Jung ,  Seunguk Han ,  Juyoung Huh

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L23/16 ,  H01L23/544

CPC classification number: H01L21/0337 ,  H01L21/0271 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/0228 ,  H01L23/16 ,  H01L23/544

Abstract: A method of manufacturing a semiconductor device includes: forming a mask layer, a first separation layer, a first mandrel layer, a second separation layer and a second mandrel layer on a substrate; patterning the second mandrel layer to form second mandrel patterns; forming first spacers on the second mandrel patterns; removing the second mandrel patterns; patterning the second separation layer and the first mandrel layer to form first structures; forming a second spacer layer on the first structures and the first separation layer; anisotropically etching the second spacer layer to form second spacers on the first structures, and to form first dummy patterns and align key patterns on the first structures; and spin-coating a spin-on hard mask layer on the first separation layer, wherein the spin-on hard mask layer covers the first structures, the first dummy patterns and the align key patterns.

公开(公告)号：US20220406786A1

公开(公告)日：2022-12-22

申请号：US17568262

申请日：2022-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongin Kang

IPC: H01L27/108

Abstract: A semiconductor device includes a substrate including a cell area and an interface area surrounding the cell area, the substrate including a device isolation layer defining an active region in the cell area and including an area isolation layer in the interface area, a gate structure extending in the cell area in a first horizontal direction, the gate structure being buried in the substrate and intersecting the active region, a bit line structure intersecting the gate structure and extending in a second horizontal direction intersecting the first horizontal direction, and dummy gate structures extending in the interface area in the first horizontal direction and being spaced apart from one another in the second horizontal direction. The dummy gate structures are buried in the area isolation layer and being spaced apart from the gate structure in the second horizontal direction.