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公开(公告)号：US20190206877A1
公开(公告)日：2019-07-04
申请号：US16125167
申请日：2018-09-07
发明人： Dong-Wan KIM , Keunnam KIM , Juik LEE
IPC分类号： H01L27/108 , H01L27/22 , H01L27/24 , H01L23/535 , G11C8/08
摘要： A semiconductor memory device includes a word line buried in an upper portion of a substrate and extending in a first direction, and a word line contact plug connected to the word line. An end portion of the word line includes a contact surface exposed in the first direction, and the word line contact plug is connected to the contact surface.
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公开(公告)号：US20230077803A1
公开(公告)日：2023-03-16
申请号：US17751740
申请日：2022-05-24
发明人： Jimin CHOI , Jongmin LEE , Yeonjin LEE , Jeonil LEE , Juik LEE , Minjung CHOI
IPC分类号： H01L23/48 , H01L23/00 , H01L25/065
摘要： A semiconductor device includes a substrate, an etch stop layer on the substrate, a through-hole electrode extending through the substrate and the etch stop layer in a vertical direction substantially perpendicular to an upper surface of the substrate, and a conductive pad. The etch stop layer includes a first surface adjacent to the substrate and a second surface opposite the first surface. The through-hole electrode includes a protrusion portion that protrudes from the second surface of the etch stop layer. The conductive pad covers the protrusion portion of the through-hole electrode. The protrusion portion of the through-hole electrode is not flat.
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公开(公告)号：US20230030117A1
公开(公告)日：2023-02-02
申请号：US17714202
申请日：2022-04-06
发明人： Juik LEE , Jong-Min LEE , Jimin CHOI , Yeonjin LEE , Jeon Il LEE
IPC分类号： H01L23/48 , H01L23/522 , H01L23/528 , H01L25/065 , H01L23/00 , H01L25/10
摘要： A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.
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公开(公告)号：US20220084885A1
公开(公告)日：2022-03-17
申请号：US17201457
申请日：2021-03-15
发明人： Junghoon HAN , Juik LEE
IPC分类号： H01L21/768 , H01L23/48 , H01L23/31
摘要： A semiconductor device includes a substrate, an interlayer insulating layer covering an upper surface of the substrate, an individual device in the interlayer insulating layer, a lower insulating layer covering a lower surface of the substrate, a through-silicon-via (TSV) structure extending through the substrate, the interlayer insulating layer and the lower insulating layer, a conductive pad connected to an upper end of the TSV structure, a via insulating layer surrounding the TSV structure, a capping insulating layer surrounding the TSV structure outside the via insulating layer. The via insulating layer and the capping insulating layer have an air gap therebetween. A portion of the air gap extends into the lower insulating layer.
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公开(公告)号：US20230078980A1
公开(公告)日：2023-03-16
申请号：US17696989
申请日：2022-03-17
发明人： Jimin CHOI , Jeonil LEE , Jongmin LEE , Juik LEE
IPC分类号： H01L25/065 , H01L23/367 , H01L23/42 , H01L23/48
摘要： A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.
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公开(公告)号：US20210375759A1
公开(公告)日：2021-12-02
申请号：US17398043
申请日：2021-08-10
发明人： Juik LEE , Joongwon SHIN , Jihoon CHANG , Junghoon HAN , Junwoo LEE
IPC分类号： H01L23/528 , H01L23/532 , H01L25/065 , H01L25/18 , H01L23/522 , H01L27/108 , H01L23/00 , H01L23/48
摘要： A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.
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公开(公告)号：US20210104462A1
公开(公告)日：2021-04-08
申请号：US16885438
申请日：2020-05-28
发明人： Juik LEE , Joongwon SHIN , Jihoon CHANG , Junghoon HAN , Junwoo LEE
IPC分类号： H01L23/528 , H01L23/48 , H01L23/532 , H01L25/065 , H01L25/18 , H01L23/522 , H01L27/108 , H01L23/00
摘要： A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.
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公开(公告)号：US20180331046A1
公开(公告)日：2018-11-15
申请号：US16026937
申请日：2018-07-03
发明人： Kiseok LEE , Sooho SHIN , Juik LEE , Jun Ho LEE , Kwangmin KIM , Ilyoung MOON , Jemin PARK , Bumseok SEO , Chan-Sic YOON , Hoin LEE
IPC分类号： H01L23/544 , H01L27/108
CPC分类号： H01L23/544 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
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