公开(公告)号：US20240332228A1

公开(公告)日：2024-10-03

申请号：US18535351

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongwon SHIN ,  Yeonjin LEE ,  Jongmin LEE ,  Jimin CHOI

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02206 ,  H01L2224/05016 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/16145

Abstract: A semiconductor device includes an insulating structure on a semiconductor substrate, lower conductive patterns in the insulating structure, upper conductive patterns on the insulating structure, conductive vias in the insulating structure and connecting at least one of the upper conductive patterns to at least one of the lower conductive patterns, a protective layer covering the insulating structure and the upper conductive patterns, an etch stop layer covering the protective layer, a first passivation layer on portions of the etch stop layer between the upper conductive patterns, and an upper passivation layer on the first passivation layer.

公开(公告)号：US20240071923A1

公开(公告)日：2024-02-29

申请号：US18209820

申请日：2023-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjun SONG ,  Jongmin LEE ,  Joongwon SHIN ,  Nara LEE ,  Jimin CHOI

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/53295 ,  H01L24/16 ,  H01L25/0657 ,  H10B80/00 ,  H01L23/53228 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor device may include lower metal wirings on a substrate, a first upper insulating interlayer on the lower metal wirings, a first upper wiring including a first upper via in the first upper insulating interlayer and a first upper metal pattern on the first upper insulating interlayer. The semiconductor device may also include a second upper insulating interlayer on the first upper insulating interlayer, an uppermost wiring including an uppermost via in the second upper insulating interlayer, an uppermost metal pattern on the second upper insulating interlayer, and an oxide layer for supplying hydrogen on the second upper insulating interlayer. The lower metal wirings may be stacked in a plurality of layers. The oxide layer for supplying hydrogen may cover the uppermost wiring. A thickness of the uppermost via may be less than 40% of a thickness of the uppermost metal pattern.

公开(公告)号：US20240038675A1

公开(公告)日：2024-02-01

申请号：US18313491

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimin CHOI ,  Joongwon SHIN ,  Sungyun WOO ,  Yeonjin LEE ,  Jongmin LEE ,  Sehyun HWANG

IPC: H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2223/54426

Abstract: A semiconductor device may include a plurality of chip regions on a substrate, at least one scribe lane surrounding each of the plurality of chip regions on the substrate, a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions, and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane.

公开(公告)号：US20240290677A1

公开(公告)日：2024-08-29

申请号：US18459111

申请日：2023-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong PARK ,  Joongwon SHIN ,  Jong-Min LEE ,  Jimin CHOI

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L23/3157 ,  H01L21/56 ,  H01L21/76801 ,  H01L23/3192 ,  H01L23/53295 ,  H01L24/13 ,  H01L23/291 ,  H01L24/05 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05669 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496

Abstract: A semiconductor device includes an interlayer insulating layer, a first protective insulating layer on the interlayer insulating layer, a second protective insulating layer on the first protective insulating layer, and insulating structures disposed in at least one of the first protective insulating layer or the second protective insulating layer, wherein the insulating structures include a first insulating structure including a first material having a first physical property, and a second insulating structure including a second material having a second physical property, and the first material and the second material include a same material, and the first physical property and the second physical property are different physical properties.

公开(公告)号：US20210375759A1

公开(公告)日：2021-12-02

申请号：US17398043

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juik LEE ,  Joongwon SHIN ,  Jihoon CHANG ,  Junghoon HAN ,  Junwoo LEE

IPC: H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L23/522 ,  H01L27/108 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.

公开(公告)号：US20210104462A1

公开(公告)日：2021-04-08

申请号：US16885438

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juik LEE ,  Joongwon SHIN ,  Jihoon CHANG ,  Junghoon HAN ,  Junwoo LEE

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L23/522 ,  H01L27/108 ,  H01L23/00

Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.