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公开(公告)号:US11812609B2
公开(公告)日:2023-11-07
申请号:US17218267
申请日:2021-03-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Byoung Il Lee , Yu Jin Seo , Jun Eon Jin
IPC: H10B43/10 , H01L23/522 , H10B41/10 , H01L23/528 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
CPC classification number: H10B43/10 , H01L23/5226 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
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公开(公告)号:US11778821B2
公开(公告)日:2023-10-03
申请号:US17037074
申请日:2020-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Joon Sung Kim , Byoung Il Lee , Seong-Hun Jeong , Jun Eon Jin
IPC: H01L27/11582 , H01L27/11565 , H01L23/528 , H01L27/1157 , H01L27/11573 , H01L23/522 , H01L27/11575 , H10B43/27 , G11C8/14 , G11C7/18 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40
CPC classification number: H10B43/27 , G11C7/18 , G11C8/14 , H01L23/5226 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40
Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.
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公开(公告)号:US20210242229A1
公开(公告)日:2021-08-05
申请号:US17218267
申请日:2021-03-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: BYOUNG IL LEE , Yu Jin Seo , Jun Eon Jin
IPC: H01L27/11565 , H01L27/11524 , H01L27/11556 , H01L23/522 , H01L27/1157 , H01L27/11582 , H01L23/528 , H01L27/11519
Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
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公开(公告)号:US20240397719A1
公开(公告)日:2024-11-28
申请号:US18791831
申请日:2024-08-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Joon Sung Kim , Byoung Il Lee , Seong-Hun Jeong , Jun Eon Jin
IPC: H10B43/27 , G11C7/18 , G11C8/14 , H01L23/522 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40
Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.
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公开(公告)号:US12058863B2
公开(公告)日:2024-08-06
申请号:US18158605
申请日:2023-01-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Joon Sung Kim , Byoung Il Lee , Seong-Hun Jeong , Jun Eon Jin
IPC: H01L27/11582 , G11C7/18 , G11C8/14 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/40
CPC classification number: H10B43/27 , G11C7/18 , G11C8/14 , H01L23/5226 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40
Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.
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公开(公告)号:US20230165005A1
公开(公告)日:2023-05-25
申请号:US18158605
申请日:2023-01-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Joon Sung Kim , Byoung Il Lee , Seong-Hun Jeong , Jun Eon Jin
IPC: H10B43/27 , G11C8/14 , H01L23/522 , G11C7/18 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40
CPC classification number: H10B43/27 , G11C8/14 , H01L23/5226 , G11C7/18 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40
Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.
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公开(公告)号:US20210265389A1
公开(公告)日:2021-08-26
申请号:US17037074
申请日:2020-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Joon Sung Kim , Byoung Il Lee , Seong-Hun Jeong , Jun Eon Jin
IPC: H01L27/11582 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11519 , H01L27/11526 , H01L23/522 , G11C7/18 , G11C8/14
Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.
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公开(公告)号:US10978465B2
公开(公告)日:2021-04-13
申请号:US16227985
申请日:2018-12-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Byoung Il Lee , Yu Jin Seo , Jun Eon Jin
IPC: H01L27/11565 , H01L27/11524 , H01L27/11556 , H01L23/522 , H01L27/1157 , H01L27/11582 , H01L23/528 , H01L27/11519
Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
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