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    DATA OUTPUT DEVICE
    2.
    发明申请
    DATA OUTPUT DEVICE 有权

    公开(公告)号：US20210404869A1

    公开(公告)日：2021-12-30

    申请号：US17473029

    申请日：2021-09-13

    Applicant: SAMSUNG ELECTRONICS CO.,LTD

    Inventor： Yun Jae SUH ,  Sung Ho KIM ,  Jun Seok KIM

    IPC: G01J1/44 ,  H03F3/45 ,  G01J1/02

    Abstract: A data output device is provided. The data output device includes a converter circuit configured to generate a conversion signal based on an output signal; a boosting circuit configured to generate a boosting signal based on the output signal; and an output circuit configured to generate the output signal based on an input signal and a feedback signal, the feedback signal being based on the conversion signal and the boosting signal.

    SYNAPSE ARRAY, PULSE SHAPER CIRCUIT AND NEUROMORPHIC SYSTEM
    6.
    发明申请
    SYNAPSE ARRAY, PULSE SHAPER CIRCUIT AND NEUROMORPHIC SYSTEM 有权
    SYNPSE阵列，脉冲形状电路和神经系统

    公开(公告)号：US20140365416A1

    公开(公告)日：2014-12-11

    申请号：US14165392

    申请日：2014-01-27

    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION ,  SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Seok KIM ,  Jae Yoon SIM ,  Hyun Surk RYU ,  Hwasuk CHO

    IPC: G06N3/063 ,  G06N3/08

    CPC classification number: G06N3/063 ,  G06N3/049 ,  G11C11/412

    Abstract: A synapse array based on a static random access memory (SRAM), a pulse shaper circuit, and a neuromorphic system are provided. The synapse array includes a plurality of synapse circuits. At least one synapse circuit among the plurality of synapse circuits includes at least one bias transistor and at least two cut-off transistors, and the at least one synapse circuit is configured to charge a membrane node of a neuron circuit connected with the at least one synapse circuit using a sub-threshold leakage current that passed through the at least one bias transistor.

    Abstract translation: 提供了基于静态随机存取存储器（SRAM），脉冲整形器电路和神经形态系统的突触阵列。 突触阵列包括多个突触电路。 所述多个突触电路中的至少一个突触电路包括至少一个偏置晶体管和至少两个截止晶体管，并且所述至少一个突触电路被配置为对与所述至少一个连接的神经元电路的膜节点进行充电 使用通过所述至少一个偏置晶体管的子阈值漏电流的突触电路。

    NEUROMORPHIC CHIP AND METHOD AND APPARATUS FOR DETECTING SPIKE EVENT
    7.
    发明申请
    NEUROMORPHIC CHIP AND METHOD AND APPARATUS FOR DETECTING SPIKE EVENT 审中-公开
    神经芯片和检测SPIKE事件的方法和装置

    公开(公告)号：US20140330761A1

    公开(公告)日：2014-11-06

    申请号：US14223284

    申请日：2014-03-24

    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION ,  Samsung Electronics Co., Ltd.

    Inventor： Jun Seok KIM ,  Jae Yoon SIM ,  Hyun Surk RYU

    IPC: G06N3/08

    CPC classification number: G06N3/063 ,  G06N3/049

    Abstract: Disclosed are a method and an apparatus for detecting spike event or transmitting spike event information generated in a neuromorphic chip. The apparatus for detecting spike event generated in a neuromorphic chip may detect spike event information for a plurality of neurons included in the neuromorphic chip based on a neuron group.

    Abstract translation: 公开了一种用于检测在神经元芯片中产生的尖峰事件或发送尖峰事件信息的方法和装置。 用于检测在神经元芯片中产生的尖峰事件的装置可以基于神经元组来检测包括在神经元芯片中的多个神经元的尖峰事件信息。

    IMAGE PROCESSING DEVICE OF VISION SENSOR
    8.
    发明申请
    IMAGE PROCESSING DEVICE OF VISION SENSOR 有权

    公开(公告)号：US20240422447A1

    公开(公告)日：2024-12-19

    申请号：US18744213

    申请日：2024-06-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Gyu Beom IM ,  Keun Joo PARK ,  Jun Seok KIM ,  Jun Hyuk PARK ,  Bong Ki SON ,  Ji Won IM

    IPC: H04N25/47 ,  H04N23/745

    Abstract: An image processing device is provided. The image processing device includes: a memory; a vision sensor; and at least one processor operatively connected to the memory and the vision sensor, wherein the at least one processor is configured to: receive an event signal from a pixel array of the vision sensor, accumulate the event signal during a preset time and store, in the memory, the event signal as accumulated event data; perform a pixel correction on the stored accumulated event data; and compare the corrected accumulated event data with the event signal to extract valid event data.

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