-
公开(公告)号:US20250107461A1
公开(公告)日:2025-03-27
申请号:US18753575
申请日:2024-06-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changyup PARK , Young Jae Kang , DongGeon Gu , Bonwon Koo , Segab Kwon , Dongho Ahn , Changseung Lee , Yongnam Ham
Abstract: Provided are variable resistance materials and a variable resistance memory devices including the same. The variable resistance memory device includes: a first electrode; a first variable resistance material on the first electrode; and a second electrode on the first variable resistance material. The first variable resistance material includes germanium, antimony, tellurium, carbon, and sulfur and is expressed by CpSqGexSbyTez, where p is an atomic concentration of carbon, q is an atomic concentration of sulfur, x is an atomic concentration of germanium, y is an atomic concentration of antimony, and z is an atomic concentration of tellurium, wherein a sum of p, q, x, y, and z equals 1, wherein each of p, q, x, y, and z is greater than zero, and wherein q is greater than 0.01 and is less than or equal to about 0.2.
-
公开(公告)号:US20250107208A1
公开(公告)日:2025-03-27
申请号:US18976637
申请日:2024-12-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Changhyun KIM , Seunggeol NAM , Keunwook SHIN , Dohyun LEE
IPC: H01L29/45 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/786
Abstract: A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.
-
公开(公告)号:US20250107201A1
公开(公告)日:2025-03-27
申请号:US18972067
申请日:2024-12-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byounghak Hong , Seunghyun Song , Kang-ill Seo , Daewon Ha , Jason Martineau
IPC: H01L29/40 , H01L21/8238 , H01L27/092 , H01L29/49
Abstract: Presented are structures and methods for forming such structures that allow for electrical or diffusion breaks between transistors of one level of a stacked transistor device, without necessarily requiring that a like electrical or diffusion break exists in another level of the stacked transistor device. Also presented, an electrical break between transistor devices may be formed by providing a channel of a first polarity with a false gate comprising a work-function metal of an opposite polarity.
-
公开(公告)号:US20250107185A1
公开(公告)日:2025-03-27
申请号:US18738197
申请日:2024-06-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyohoon BYEON , Seokhoon Kim , Pankwi Park , Sungkeun Lim , Yuyeong Jo
IPC: H01L29/08 , H01L21/02 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, and including a plurality of semiconductor patterns spaced apart from each other and vertically stacked, a gate electrode on the plurality of semiconductor patterns, and extending in a first horizontal direction, a gate spacer disposed on a sidewall of the gate electrode in a second horizontal direction crossing the first horizontal direction, a source/drain pattern electrically connected to the plurality of semiconductor patterns, and including a first epitaxial pattern and a second epitaxial pattern on a side surface of the first epitaxial pattern in the second horizontal direction, and a protection pattern between at least one of the plurality of semiconductor patterns and the gate spacer and including a material having an etch selectivity with the first epitaxial pattern.
-
公开(公告)号:US20250107172A1
公开(公告)日:2025-03-27
申请号:US18974171
申请日:2024-12-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Byounghak Hong , Seungchan Yun , Kang-ill Seo
IPC: H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
Abstract: A multi-stack semiconductor device includes: a substrate; a multi-stack transistor formed on the substrate and including a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor, wherein the nanosheet transistor includes a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers, the FinFET includes at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and each of the lower and upper gate structures includes: a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and a gate metal pattern formed on the gate oxide layer. At least one of the lower and upper gate structures includes an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.
-
公开(公告)号:US20250107160A1
公开(公告)日:2025-03-27
申请号:US18625801
申请日:2024-04-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Joonseok Kim , Sangwon KIM , CHANG SEOK LEE , Huije Ryu , KEUN WOOK SHIN
IPC: H01L29/76
Abstract: A transistor including a semiconductor channel including a compound semiconductor, and a source electrode and a drain electrode each electrically connected to the semiconductor channel and each independently including a topological conductor, wherein the compound semiconductor and the topological conductor include at least one metal element in common.
-
公开(公告)号:US20250107086A1
公开(公告)日:2025-03-27
申请号:US18737295
申请日:2024-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hanbyeol LEE , Younghwan SON , Sangdon LEE , Shinhwan KANG , Sukkang SUNG
Abstract: A semiconductor device includes gate electrodes stacked and spaced apart from each other including upper gate electrodes, memory gate electrodes and lower gate electrodes sequentially stacked from the horizontal conductive layer; a horizontal connection portion between the memory gate electrodes and the lower gate electrodes; channel structures penetrating through the gate electrodes and extending in the first direction in the first region; isolation regions penetrating through the gate electrodes; an insulating region extending from a lowermost surface of the gate electrodes and penetrating through at least one of the lower gate electrodes between the isolation regions; wherein an upper surface of the insulating region has a first width, a lower surface has a second width greater than the first width, an upper surface of each of the channel structures has a third width, and a lower surface has a fourth width smaller than the third width.
-
公开(公告)号:US20250107022A1
公开(公告)日:2025-03-27
申请号:US18907611
申请日:2024-10-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jooyoung KANG , Bongsoo KIM , Sejin PARK , Wanju BYUN , Sujeong CHO , Hyunju HONG
IPC: H05K5/02
Abstract: An electronic device includes a first housing, a second housing slidably coupled to the first housing, and a drive part. The drive part provides a driving force for sliding the second housing and includes a pinion gear and a drive motor configured to rotate the pinion gear. The electronic device further includes a rack gear and a guide structure. The rack gear is gear-coupled to the pinion gear to reciprocate in a predetermined section in accordance with a rotation of the pinion gear. The guide structure includes an accommodation space configured to accommodate at least a part of the rack gear and to guide the moving rack gear.
-
公开(公告)号:US20250107012A1
公开(公告)日:2025-03-27
申请号:US18903540
申请日:2024-10-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hwanju JEON
Abstract: An electronic device according to an embodiment of the disclosure may include: a housing including a coupling part configured to be be detachably coupled to a ring-shaped external device, wherein the coupling part includes a first coupling surface, a second coupling surface extending from one side of the first coupling surface, a third coupling surface extending from an other side of the first coupling surface, and a connection terminal formed on at least one of the first coupling surface, the second coupling surface, and the third coupling surface and configured to electrically connect the electronic device with the external device based on the electronic device being coupled to the external device, and based on the electronic device being coupled with the external device, the first coupling surface is disposed to face an outer surface facing in a direction opposite to an inner surface of the external device, and the second coupling surface and the third coupling surface are arranged to face a side surface formed between the inner surface and the outer surface of the external device.
-
10.
公开(公告)号:US20250106873A1
公开(公告)日:2025-03-27
申请号:US18899008
申请日:2024-09-27
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jeongseok YU , Hyunjeong KANG , Taeseop LEE
IPC: H04W72/25 , H04L1/1812 , H04L5/00 , H04W72/566
Abstract: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. A method performed by a terminal for SL communication is provided, which includes receiving, from a base station, an SL grant for SL transmission; in case that there is an SL-PRS for transmission for a selected destination, identifying a first TBS including the SL-PRS based on the SL grant; and in case that all data within a logical channel with higher priority than a logical channel of the SL-PRS is allocated with resources of the SL grant, transmitting the SL-PRS based on the SL grant.
-
-
-
-
-
-
-
-
-