公开(公告)号：US20210020695A1

公开(公告)日：2021-01-21

申请号：US16789546

申请日：2020-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon BAK ,  Woojin KIM ,  Junghwan MOON ,  Seowon LEE ,  Nayoung JI

IPC: H01L27/24 ,  H01L27/22 ,  G11C13/00

Abstract: A variable resistance memory device includes a first conductive line, a bipolar selection device on the first conductive line and electrically connected to the first conductive line, a second conductive line on the first conductive line and electrically connected to the bipolar selection device, a variable resistance layer on the second conductive line and electrically connected to the second conductive line, and a third conductive line on the variable resistance layer and electrically connected to the variable resistance layer.

公开(公告)号：US20240324243A1

公开(公告)日：2024-09-26

申请号：US18473660

申请日：2023-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjae KIM ,  Woojin KIM ,  Junghoon BAK ,  Hyunchul SHIN ,  Hyeonah JO

IPC: H10B61/00 ,  H01L23/522

CPC classification number: H10B61/22 ,  H01L23/5226

Abstract: A semiconductor device includes a plurality of data storage patterns on a substrate, the plurality of data storage patterns spaced apart from each other in a first direction parallel to an upper surface of the substrate, a first upper conductive line on the plurality of data storage patterns, extending in the first direction and connected to the plurality of data storage patterns, a second upper conductive line on the first upper conductive line and extending in the first direction and a plurality of via contacts between the first upper conductive line and the second upper conductive line and spaced apart from each other in the first direction. The plurality of via contacts are arranged to be offset from the plurality of data storage patterns in the first direction.

公开(公告)号：US20210050508A1

公开(公告)日：2021-02-18

申请号：US16829216

申请日：2020-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seowon LEE ,  Junghwan MOON ,  Junghoon BAK ,  Woojin KIM ,  Hyeongsun HONG

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01F10/32

Abstract: A magnetic memory device includes a device isolation layer on a substrate and defining an active region, a source region and a drain region apart from each other in the active region of the substrate, a channel portion in the active region of the substrate and between the source region and the drain region, a spin orbit torque (SOT)-inducing layer on the channel portion of the substrate, a magnetic tunnel junction (MTJ) structure on the SOT-inducing layer, the MTJ structure including a free layer on the SOT-inducing layer, a tunnel barrier layer on the free layer, and a pinned layer on the tunnel barrier, a word line on the MTJ structure, a source line electrically connected to the source region, and a bit line electrically connected to the drain region.