公开(公告)号：US11705379B2

公开(公告)日：2023-07-18

申请号：US17087879

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Lee ,  Won Kim ,  Haeseok Park ,  Ilgeun Jung ,  Jinkuk Bae ,  Inyoung Lee ,  Sungdong Cho

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L22/12 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/13016 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/14515 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/1436

Abstract: A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.

公开(公告)号：US11923292B2

公开(公告)日：2024-03-05

申请号：US17307212

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkuk Bae ,  Hyunsoo Chung ,  Inyoung Lee ,  Donghyeon Jang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5226 ,  H01L21/76873 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

公开(公告)号：US20230387005A1

公开(公告)日：2023-11-30

申请号：US18201995

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok Ahn ,  Jinkuk Bae

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/7682 ,  H01L23/53266

Abstract: A semiconductor device includes a first contact structure connected to the lower structure, a first conductive wiring connected to the first contact structure, a first etch-stop layer and an interlayer insulating layer sequentially provided on the first conductive wiring, a second contact structure passing through the first etch-stop layer, provided in the interlayer insulating layer, and connected to the first conductive wiring, a second conductive wiring provided on the second contact structure and provided in the interlayer insulating layer, a barrier layer including a first barrier portion on a bottom surface of the second contact structure, a second etch-stop layer provided on a top surface of the second conductive wiring and a top surface of the interlayer insulating layer, and an air gap between the barrier layer and the extension portion.

公开(公告)号：US11024575B2

公开(公告)日：2021-06-01

申请号：US16415469

申请日：2019-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkuk Bae ,  Hyunsoo Chung ,  Inyoung Lee ,  Donghyeon Jang

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.