公开(公告)号：US20240120354A1

公开(公告)日：2024-04-11

申请号：US18371258

申请日：2023-09-21

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Kyong Soon CHO

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14618 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/14621 ,  H01L27/14685 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L27/14627 ,  H01L27/1464 ,  H01L2224/05551 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06155 ,  H01L2224/06515 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29035 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/83986 ,  H01L2224/92165 ,  H01L2224/92247 ,  H01L2924/0665

Abstract: A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, a transparent substrate on the semiconductor chip, a dam structure between the semiconductor chip and the transparent substrate, a dummy pad on a lower side of the dam structure and to which no wiring is connected, a planarization film extending along an upper surface of the semiconductor chip and a passivation film on the planarization film, wherein the planarization film is spaced apart from the dam structure.

公开(公告)号：US20180337120A1

公开(公告)日：2018-11-22

申请号：US15795448

申请日：2017-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyong Soon CHO ,  Jae Eun LEE

IPC: H01L23/50

CPC classification number: H01L23/50 ,  H01L2924/1431

Abstract: A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces.

公开(公告)号：US20190221513A1

公开(公告)日：2019-07-18

申请号：US16359307

申请日：2019-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyong Soon CHO ,  Jae Eun LEE

IPC: H01L23/50 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces.

公开(公告)号：US20190206807A1

公开(公告)日：2019-07-04

申请号：US16109766

申请日：2018-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyong Soon CHO

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/36

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/17181

Abstract: A semiconductor package includes a first substrate having a first surface and a second surface opposite to the first surface, a first semiconductor chip on the first surface of the first substrate, a second semiconductor chip on the first surface of the first, a stiffener on the first semiconductor chip and the second semiconductor chip, and an encapsulant on the first surface of the first substrate. The first substrate includes a plurality of first pads on the first surface thereof and a plurality of second pads on the second surface thereof. The first semiconductor chip is connected to a first group of first pads of the plurality of first pads. The second semiconductor chip is connected to a second group of first pads of the plurality of first pads. The stiffener covers a space between the first semiconductor chip and the second semiconductor chip. The encapsulant covers at least a sidewall of each of the first and second semiconductor chips and the stiffener.