公开(公告)号：US20240332241A1

公开(公告)日：2024-10-03

申请号：US18744174

申请日：2024-06-14

申请人： SK hynix Inc.

发明人： Jin Woong KIM ,  Mi Seon LEE

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/30 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05186 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/14134 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2746 ,  H01L2224/29012 ,  H01L2224/29035 ,  H01L2224/29147 ,  H01L2224/29186 ,  H01L2224/3003 ,  H01L2224/30051 ,  H01L2224/3015 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/30517 ,  H01L2224/30519 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/81201 ,  H01L2224/83048 ,  H01L2224/83201 ,  H01L2924/04941 ,  H01L2924/05042

摘要： A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.

公开(公告)号：US20180175012A1

公开(公告)日：2018-06-21

申请号：US15665495

申请日：2017-08-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC分类号： H01L25/00 ,  H01L23/58 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L23/3114 ,  H01L23/564 ,  H01L23/585 ,  H01L24/29 ,  H01L24/66 ,  H01L24/69 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/1162 ,  H01L2224/11845 ,  H01L2224/13147 ,  H01L2224/17517 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/2761 ,  H01L2224/2762 ,  H01L2224/27845 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29015 ,  H01L2224/29019 ,  H01L2224/29035 ,  H01L2224/29147 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83193 ,  H01L2224/83815 ,  H01L2224/83895 ,  H01L2224/8392 ,  H01L2224/83935 ,  H01L2224/83951 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A three-dimensional (3D) integrated circuit (IC) includes a first IC die and a second IC die. The first IC die includes a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

公开(公告)号：US09385099B2

公开(公告)日：2016-07-05

申请号：US14229717

申请日：2014-03-28

申请人： NXP B.V.

发明人： Leonardus Antonius Elisabeth van Gemert ,  Coenraad Cornelis Tak ,  Marten Oldsen ,  Hendrik Bouman

IPC分类号： H01L21/44 ,  H01L23/66 ,  H01L23/58 ,  H01L23/00 ,  B81B7/00

CPC分类号： H01L24/17 ,  B81B7/0048 ,  B81B7/007 ,  H01L24/11 ,  H01L24/14 ,  H01L24/73 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/1401 ,  H01L2224/14134 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/26165 ,  H01L2224/26175 ,  H01L2224/29013 ,  H01L2224/29035 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/81855 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2924/35 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

摘要： One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.

摘要翻译： 一个示例性实施例公开了一种具有芯片面积的芯片，其中芯片区域包括：突出区域; 刚性联接区域，具有位于所述伸出区域的一侧上的一组刚性联接点; 以及柔性联接区域，其具有一组柔性联接点，位于与刚性联接区域相对的伸出区域的一侧。 另一示例性实施例公开了一种用于制造管芯互连的方法，包括：在具有芯片面积的芯片内制造具有一组刚性耦合点的刚性耦合器区域; 限定所述芯片区域内的伸出区域并与所述刚性耦合器区域邻接; 以及在与所述刚性耦合器区域相对的所述伸出区域的一侧的所述芯片区域内制造具有一组柔性耦合点的柔性耦合器区域。

公开(公告)号：US20150221602A1

公开(公告)日：2015-08-06

申请号：US14421689

申请日：2013-07-31

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Abdelkader Aliane ,  Romain Coppard ,  Jamal Tallal

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  H01L21/4867 ,  H01L21/563 ,  H01L23/145 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/02175 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/10156 ,  H01L2224/10175 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11515 ,  H01L2224/11848 ,  H01L2224/13007 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13187 ,  H01L2224/1601 ,  H01L2224/16505 ,  H01L2224/29035 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81121 ,  H01L2224/81192 ,  H01L2224/8123 ,  H01L2224/81409 ,  H01L2224/818 ,  H01L2224/8184 ,  H01L2224/819 ,  H01L2224/81948 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/053 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/20754 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A method of manufacturing a microelectronic device including a first component hybridized with a second component via electric interconnects, involves the steps of: (i) forming the first and second components, the second component being transparent to ultraviolet radiation at least in line with locations provided for the interconnects; (ii) forming interconnection elements including copper oxide on the second component at the locations provided for the interconnects; (iii) placing the first and second components on each other; and (iv) applying the ultraviolet radiation through the second component on the elements including copper oxide to implement an ultraviolet anneal converting copper oxide into copper.

摘要翻译： 制造包括通过电互连与第二部件杂交的第一部件的微电子器件的方法包括以下步骤：（i）形成第一和第二部件，第二部件至少与所提供的位置一致地对紫外线辐射是透明的 用于互连; （ii）在为互连设置的位置处在第二部件上形成包括氧化铜的互连元件; （iii）将第一和第二组分彼此放置; 和（iv）通过第二组分将紫外线辐射施加到包括氧化铜的元件上，以实现将铜氧化物转化为铜的紫外线退火。

公开(公告)号：US08866289B2

公开(公告)日：2014-10-21

申请号：US13344070

申请日：2012-01-05

申请人： Thorbjorn Ebefors ,  Edward Kalvesten ,  Niklas Svedin ,  Anders Eriksson

发明人： Thorbjorn Ebefors ,  Edward Kalvesten ,  Niklas Svedin ,  Anders Eriksson

IPC分类号： H01L23/10 ,  H01L23/12 ,  B81C1/00 ,  H01L23/00

CPC分类号： H01L23/10 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13144 ,  H01L2224/29035 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/83805 ,  H01L2224/9211 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/0401

摘要： A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.

摘要翻译： 一种用于接合具有单片集成部件的半导体晶片的密封和接合材料结构。 密封和接合材料设置成形成闭环的条带。 在一个晶片上提供至少两个同心密封条。 条带布置成围绕晶片上的部件以在晶片接合在一起时被密封。 条带中的材料是将半导体晶片粘合在一起的材料，并且在受到力和任选加热时密封单片集成部件。 包括与密封和结合结构结合在一起的第一基板和第二基板的单片集成电和/或机械和/或流体和/或光学装置，以及在至少一个 描述了两个晶片并施加力并且可选地加热到晶片以连接它们。

公开(公告)号：US08773583B2

公开(公告)日：2014-07-08

申请号：US13086830

申请日：2011-04-14

申请人： Satoru Wakiyama ,  Hiroshi Ozaki

发明人： Satoru Wakiyama ,  Hiroshi Ozaki

IPC分类号： H04N5/225

CPC分类号： H01L27/14636 ,  H01L21/56 ,  H01L21/563 ,  H01L23/31 ,  H01L24/05 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L27/14605 ,  H01L27/14609 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14634 ,  H01L27/14683 ,  H01L27/1469 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83104 ,  H01L2224/83365 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15788 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

摘要： Disclosed herein is a semiconductor device including: a first semiconductor chip having an electronic circuit section and a first connecting section formed on one surface thereof; a second semiconductor chip having a second connecting section formed on one surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the first and the second connecting sections connected to each other by a bump; a dam formed to fill a gap between the first and the second semiconductor chips on a part of an outer edge of the second semiconductor chip, the part of the outer edge being on a side of a region of formation of the electronic circuit section; and an underfill resin layer filled into the gap, protrusion of the resin layer from the outer edge of the second semiconductor chip to a side of the electronic circuit section being prevented by the dam.

摘要翻译： 本发明公开了一种半导体器件，包括：具有电子电路部分的第一半导体芯片和在其一个表面上形成的第一连接部分; 具有在其一个表面上形成的第二连接部分的第二半导体芯片，所述第二半导体芯片安装在所述第一半导体芯片上，所述第一和第二连接部分通过凸块相互连接; 形成为在所述第二半导体芯片的外缘的一部分上填充所述第一和第二半导体芯片之间的间隙的坝，所述外边缘的一部分位于所述电子电路部的形成区域的一侧; 并且填充到间隙中的底部填充树脂层，树脂层从第二半导体芯片的外边缘突出到电子电路部分的侧面被大坝阻止。

公开(公告)号：US08664773B2

公开(公告)日：2014-03-04

申请号：US13477524

申请日：2012-05-22

申请人： Atsushi Yamaguchi ,  Hideyuki Tsujimura ,  Hiroe Kowada ,  Ryo Kuwabara ,  Naomichi Ohashi

发明人： Atsushi Yamaguchi ,  Hideyuki Tsujimura ,  Hiroe Kowada ,  Ryo Kuwabara ,  Naomichi Ohashi

IPC分类号： H01L21/58 ,  H01L21/60 ,  H01L23/488

CPC分类号： H01L23/315 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16238 ,  H01L2224/29017 ,  H01L2224/29035 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/2919 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83862 ,  H01L2224/9221 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/0665

摘要： A manufacturing method for a mounting structure of a semiconductor package component, including: applying a first adhesive with viscosity η1 and a thixotropy index T1 at a position on the substrate, which is on an outer side of the mounted semiconductor package component; applying, on the first adhesive, a second adhesive with viscosity η2 and a thixotropy index T2 so that the second adhesive gets in contact with an outer periphery part of the semiconductor package component; and forming, through a subsequent reflow process, a first adhesive part of the hardened first adhesive and a second adhesive part of the hardened second adhesive, wherein the first and second adhesives satisfy 30≦η2≦η1≦300 (Pa·s) and 3≦T2≦T1≦7, and sectional area S1 of the first adhesive part and sectional area S2 of the second adhesive part with respect to a direction perpendicular to a mounting surface of the substrate satisfy a relation S1≦S2.

摘要翻译： 一种半导体封装件的安装结构的制造方法，包括：在安装的半导体封装部件的外侧的基板上的位置处施加粘度eta1和触变指数T1的第一粘合剂; 在第一粘合剂上施加具有粘度eta2和触变指数T2的第二粘合剂，使得第二粘合剂与半导体封装部件的外周部分接触; 并且通过随后的回流工艺形成所述硬化的第一粘合剂的第一粘合部分和所述硬化的第二粘合剂的第二粘合部分，其中所述第一和第二粘合剂满足30（Pa·s）和3 @ T2 @ T1 @ 7，第一粘合部分的截面面积S1和第二粘合部分相对于垂直于基板的安装表面的方向的截面面积S2满足关系S1 @ S2。

公开(公告)号：US08487437B2

公开(公告)日：2013-07-16

申请号：US12885233

申请日：2010-09-17

申请人： Peter Elenius ,  Deok Hoon Kim ,  Young Sang Cho

发明人： Peter Elenius ,  Deok Hoon Kim ,  Young Sang Cho

IPC分类号： H01L23/48

CPC分类号： H01L23/10 ,  H01L23/3128 ,  H01L23/564 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2224/13 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/14155 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29035 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32 ,  H01L2224/32227 ,  H01L2224/32503 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83447 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/9211 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15321 ,  H01L2924/15788 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/73103 ,  H01L2924/00012 ,  H01L2924/00

摘要： An electronic device package includes a substrate assembly, an electronic device disposed to face the substrate assembly, and a sealing ring or rings including a sealing layer and a bonding layer that is disposed between the substrate assembly and the electronic device, wherein the sealing ring(s) has a closed loop shape surrounding a sealing region of the electronic device, and the bonding layer is formed through a reaction of the sealing layer and sealing layer pad with a low-melting-point material layer whose melting point is lower than that of the sealing layer and sealing ring pad. The bonding layer is formed of an intermetallic compound of the sealing layer, sealing ring pad and low-melting-point material that melts at a temperature greater than the melting temperature of the low-melting-point material. The device package also includes electrical connections in the form of joints between the substrate assembly and electronic device.

摘要翻译： 电子器件封装包括衬底组件，设置为面对衬底组件的电子器件，以及密封环或环，其包括设置在衬底组件和电子器件之间的密封层和接合层，其中密封环 s）具有围绕电子器件的密封区域的闭环形状，并且通过密封层和密封层焊盘与熔点低于熔点的低熔点材料层的反应形成接合层 密封层和密封环垫。 接合层由密封层，密封环垫和低熔点材料的金属间化合物形成，其熔点高于低熔点材料的熔融温度。 器件封装还包括在衬底组件和电子器件之间的接合形式的电连接。

公开(公告)号：US20120319261A1

公开(公告)日：2012-12-20

申请号：US13163935

申请日：2011-06-20

申请人： Cody B. Moody

发明人： Cody B. Moody

IPC分类号： H01L23/02 ,  H01L21/50

CPC分类号： H01L24/83 ,  H01L21/563 ,  H01L23/10 ,  H01L24/03 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/26135 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29609 ,  H01L2224/29611 ,  H01L2224/29624 ,  H01L2224/29644 ,  H01L2224/29686 ,  H01L2224/32055 ,  H01L2224/32148 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/83054 ,  H01L2224/8309 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83825 ,  H01L2224/83948 ,  H01L2224/94 ,  H01L2924/01032 ,  H01L2924/01322 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

摘要翻译： 密封的半导体晶片封装，其包括在第一晶片上的第一结合环，其面向第二晶片上的第二结合环的互补表面。 该封装包括形成在第一结合环的表面上的第一材料的第一和第二间隔，第一和第二间隔具有第一厚度。 该封装还包括共晶合金（不一定是共晶的，通常它是一种不是特定于元素的共晶比的合金），由第二种材料形成，并且第一种材料在第一和第二种之间形成气密封 晶片，通过将第一和第二晶片加热到高于第二材料的回流温度并低于第一材料的回流温度的温度而形成的共晶合金，其中共晶合金填充第一和第二间隙之间的体积， 和第二结合环，并且其中所述支架在所述第一结合环和所述第二结合环之间保持预定的距离。

公开(公告)号：US20120261809A1

公开(公告)日：2012-10-18

申请号：US13446954

申请日：2012-04-13

申请人： Yu-Lin YEN ,  Kuo-Hua LIU ,  Yu-Lung HUANG ,  Tsang-Yu LIU ,  Yen-Shih HO

发明人： Yu-Lin YEN ,  Kuo-Hua LIU ,  Yu-Lung HUANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC分类号： H01L23/04 ,  H01L21/50

CPC分类号： H01L24/29 ,  H01L23/10 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29076 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83871 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

摘要翻译： 本发明的实施例提供一种芯片封装的制造方法，包括：提供具有由多个划线分开的多个器件区域的半导体晶片; 将封装衬底接合到半导体晶片，其中间隔层设置在其间并限定分别暴露器件区域并且间隔层具有多个与半导体晶片的边缘相邻的通孔的空腔; 在通孔中填充粘合剂材料，其中间隔层的材料是粘合剂并且不同于粘合剂材料; 并且沿着划线切割半导体晶片，封装衬底和间隔层，以形成彼此分离的多个芯片封装。