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    BLOCK CLEANUP: PAGE RECLAMATION PROCESS TO REDUCE GARBAGE COLLECTION OVERHEAD IN DUAL-PROGRAMMABLE NAND FLASH DEVICES
    1.
    发明申请
    BLOCK CLEANUP: PAGE RECLAMATION PROCESS TO REDUCE GARBAGE COLLECTION OVERHEAD IN DUAL-PROGRAMMABLE NAND FLASH DEVICES 审中-公开

    公开(公告)号：US20170344307A1

    公开(公告)日：2017-11-30

    申请号：US15405227

    申请日：2017-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Narges SHAHIDI ,  Manu AWASTHI ,  Tameesh SURI ,  Vijay BALAKRISHNAN

    IPC: G06F3/06

    Abstract: According to one general aspect, an apparatus may include a memory, an erasure-based, non-volatile memory, and a processor. The memory may be configured to store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The erasure-based, non-volatile memory may be configured to store information, at respective memory addresses, in an encoded format. The encoded format may include more bits than the unencoded version of the information and the encoded format may allow the information be over-written, at least once, without an intervening erase operation. The processor may be configured to perform garbage collection based, at least in part upon, the rewriteable state associated with the respective memory addresses.

    DATA MANAGEMENT SCHEME IN VIRTUALIZED HYPERSCALE ENVIRONMENTS
    2.
    发明申请
    DATA MANAGEMENT SCHEME IN VIRTUALIZED HYPERSCALE ENVIRONMENTS 审中-公开

    公开(公告)号：US20190146670A1

    公开(公告)日：2019-05-16

    申请号：US16231229

    申请日：2018-12-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Manu AWASTHI ,  Robert BRENNAN

    IPC: G06F3/06

    Abstract: According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.

    BLOCK CLEANUP: PAGE RECLAMATION PROCESS TO REDUCE GARBAGE COLLECTION OVERHEAD IN DUAL-PROGRAMMABLE NAND FLASH DEVICES
    3.
    发明申请
    BLOCK CLEANUP: PAGE RECLAMATION PROCESS TO REDUCE GARBAGE COLLECTION OVERHEAD IN DUAL-PROGRAMMABLE NAND FLASH DEVICES 审中-公开

    公开(公告)号：US20200278805A1

    公开(公告)日：2020-09-03

    申请号：US16875986

    申请日：2020-05-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Narges SHAHIDI ,  Manu AWASTHI ,  Tameesh SURI ,  Vijay BALAKRISHNAN

    IPC: G06F3/06

    Abstract: According to one general aspect, an apparatus may include a memory, an erasure-based, non-volatile memory, and a processor. The memory may be configured to store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The erasure-based, non-volatile memory may be configured to store information, at respective memory addresses, in an encoded format. The encoded format may include more bits than the unencoded version of the information and the encoded format may allow the information be over-written, at least once, without an intervening erase operation. The processor may be configured to perform garbage collection based, at least in part upon, the rewriteable state associated with the respective memory addresses.

    ADDRESS TRANSLATION IN MEMORY
    4.
    发明申请
    ADDRESS TRANSLATION IN MEMORY 审中-公开
    存储器中的地址翻译

    公开(公告)号：US20160147667A1

    公开(公告)日：2016-05-26

    申请号：US14813111

    申请日：2015-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Manu AWASTHI ,  Kevin CHANG

    IPC: G06F12/10 ,  G06F12/14

    CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F12/1425 ,  G06F12/1491 ,  G06F15/7821 ,  G06F2212/1052 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/684 ,  Y02D10/12 ,  Y02D10/13

    Abstract: According to one general aspect, a computational memory may include memory cells configured to store data and a page table, wherein the page table maps, at least in part, a virtual address to a physical address. The computational memory may also include at least one processor-in-memory. Each processor-in-memory may be configured to: receive a request to execute an instruction utilizing the portion of the data stored by the memory cells, wherein the request includes the virtual address, request the physical address from a translator, and execute the instruction utilizing the physical address. The computational memory may further include the translator which may be configured to, for each processor-in-memory, convert, by accessing the page table, a virtual address associated with a portion of the data to a physical address associated with the portion of the data.

    Abstract translation: 根据一个一般方面，计算存储器可以包括被配置为存储数据的存储单元和页表，其中页表至少部分地映射到物理地址的虚拟地址。 计算存储器还可以包括至少一个存储器处理器。 每个存储器处理器可以被配置为：使用存储器单元存储的数据的一部分来接收执行指令的请求，其中所述请求包括虚拟地址，从翻译器请求物理地址，并执行指令 利用物理地址。 计算存储器还可以包括翻译器，其可以被配置为，对于每个处理器在存储器中，通过访问页表将与数据的一部分相关联的虚拟地址转换成与所述页表的一部分相关联的物理地址 数据。

    DATA MANAGEMENT SCHEME IN VIRTUALIZED HYPERSCALE ENVIRONMENTS
    5.
    发明申请
    DATA MANAGEMENT SCHEME IN VIRTUALIZED HYPERSCALE ENVIRONMENTS 审中-公开

    公开(公告)号：US20200301582A1

    公开(公告)日：2020-09-24

    申请号：US16897264

    申请日：2020-06-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Manu AWASTHI ,  Robert BRENNAN

    IPC: G06F3/06

    Abstract: According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.

    MULTI-BIT DATA REPRESENTATION FRAMEWORK TO ENABLE DUAL PROGRAM OPERATION ON SOLID-STATE FLASH DEVICES
    6.
    发明申请
    MULTI-BIT DATA REPRESENTATION FRAMEWORK TO ENABLE DUAL PROGRAM OPERATION ON SOLID-STATE FLASH DEVICES 审中-公开

    公开(公告)号：US20170344487A1

    公开(公告)日：2017-11-30

    申请号：US15217964

    申请日：2016-07-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Narges SHAHIDI ,  Tameesh SURI ,  Manu AWASTHI ,  Vijay BALAKRISHNAN

    IPC: G06F12/10

    Abstract: According to one general aspect, an apparatus may include a host interface, a memory, a processor, and an erasure-based, non-volatile memory. The host interface may receive a write command, wherein the write command includes unencoded data. The memory may store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The processor may select a memory address to store information included by the unencoded data based, at least in part, upon the rewriteable state of the memory address. The erasure-based, non-volatile memory may store, at the memory address, the unencoded data's information as encoded data, wherein the encoded data includes more bits than the unencoded data and wherein the encoded data can be over-written with a second unencoded data without an intervening erase operation.

    HIGH BANDWIDTH PEER-TO-PEER SWITCHED KEY-VALUE CACHING
    8.
    发明申请
    HIGH BANDWIDTH PEER-TO-PEER SWITCHED KEY-VALUE CACHING 有权
    高速带对等交换键值缓存

    公开(公告)号：US20160094638A1

    公开(公告)日：2016-03-31

    申请号：US14595172

    申请日：2015-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tameesh SURI ,  Manu AWASTHI

    IPC: H04L29/08

    CPC classification number: H04L67/104 ,  H04L47/193 ,  H04L67/2842 ,  H04L69/321

    Abstract: Inventive aspects include a high bandwidth peer-to-peer switched key-value system, method, and section. The system can include a high bandwidth switch, multiple network interface cards communicatively coupled to the switch, one or more key-value caches to store a plurality of key-values, and one or more memory controllers communicatively coupled to the key-value caches and to the network interface cards. The memory controllers can include a key-value peer-to-peer logic section that can coordinate peer-to-peer communication between the memory controllers and the multiple network interface cards through the switch. The system can further include multiple transmission control protocol (TCP) offload engines that are each communicatively coupled to a corresponding one of the network interface cards. Each of the TCP offload engines can include a packet peer-to-peer logic section that can coordinate the peer-to-peer communication between the memory controllers and the network interface cards through the switch.

    Abstract translation: 发明方面包括高带宽对等交换键值系统，方法和部分。 系统可以包括高带宽交换机，通信地耦合到交换机的多个网络接口卡，用于存储多个键值的一个或多个键值高速缓存以及通信地耦合到键值高速缓存的一个或多个存储器控制器，以及 到网络接口卡。 存储器控制器可以包括键值对等逻辑部分，其可以通过交换机来协调存储器控制器和多个网络接口卡之间的对等通信。 该系统还可以包括多个传输控制协议（TCP）卸载引擎，它们通信地耦合到相应的一个网络接口卡。 每个TCP卸载引擎可以包括分组对等逻辑部分，其可以通过交换机协调存储器控制器和网络接口卡之间的对等通信。

    DATA MANAGEMENT SCHEME IN VIRTUALIZED HYPERSCALE ENVIRONMENTS
    9.
    发明公开
    DATA MANAGEMENT SCHEME IN VIRTUALIZED HYPERSCALE ENVIRONMENTS 审中-公开

    公开(公告)号：US20230315293A1

    公开(公告)日：2023-10-05

    申请号：US18206068

    申请日：2023-06-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Manu AWASTHI ,  Robert BRENNAN

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/0685

    Abstract: According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums.

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