Volatile memory device and methods of operating and testing volatile memory device
    1.
    发明授权
    Volatile memory device and methods of operating and testing volatile memory device 有权
    易失性存储器件以及操作和测试易失性存储器件的方法

    公开(公告)号:US09552210B2

    公开(公告)日:2017-01-24

    申请号:US14101374

    申请日:2013-12-10

    Abstract: A method is provided for operating a volatile memory device. The method includes performing a first initialization operation for the volatile memory device based on a boot code received from an external memory controller, storing the boot code in an internal register, reading the boot code stored in the internal register based on a first signal received from the external memory controller when the first initialization operation is not normally performed, and performing a second initialization operation for the volatile memory device based on the boot code read from the internal register.

    Abstract translation: 提供了一种用于操作易失性存储器件的方法。 该方法包括:根据从外部存储器控制器接收到的引导代码对易失性存储器件执行第一初始化操作,将引导代码存储在内部寄存器中,基于从第一信号接收到的第一信号读取存储在内部寄存器中的引导代码 当第一初始化操作不正常地执行时,外部存储器控制器,以及基于从内部寄存器读取的引导代码对易失性存储器件执行第二初始化操作。

    Semiconductor memory device for use in multi-chip package
    2.
    发明授权
    Semiconductor memory device for use in multi-chip package 有权
    半导体存储器件用于多芯片封装

    公开(公告)号:US09230610B2

    公开(公告)日:2016-01-05

    申请号:US14336689

    申请日:2014-07-21

    Abstract: Provides is a multi-chip package including a plurality of semiconductor memory devices. Each of semiconductor memory devices includes a register and a control circuit. The register is configured to store start sequence information representing start of execution of a refresh operation in the multi-chip package. The control circuit is configured to control start of the execution of the refresh operation in response to the start sequence information stored in the register. Since the start of the execution of the refresh operation is performed in sequence of respective semiconductor memory devices according to the start sequence information stored in the register, consumption of peak current may be reduced in a power saving mode.

    Abstract translation: 提供一种包括多个半导体存储器件的多芯片封装。 每个半导体存储器件包括寄存器和控制电路。 寄存器被配置为存储表示在多芯片封装中执行刷新操作的开始顺序信息。 控制电路被配置为响应于存储在寄存器中的开始顺序信息来控制刷新操作的执行开始。 由于根据存储在寄存器中的开始顺序信息按照各个半导体存储器件的顺序执行刷新操作的开始,所以在省电模式下可以降低峰值电流的消耗。

Patent Agency Ranking