公开(公告)号：US20140129903A1

公开(公告)日：2014-05-08

申请号：US14069588

申请日：2013-11-01

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyun-Jun YOON ,  Jae-Yong JEONG ,  Myung-Hoon CHOI ,  Bo-Geun KIM ,  Ki-Tae PARK,

IPC: G11C16/26 ,  G06F11/10

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G06F11/1072 ,  G11C16/0483 ,  G11C29/00

Abstract: A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.

Abstract translation: 一种操作存储器件的方法包括将确定第一电压状态或第二电压状态的第一读取电压改变为第一范围内的电压并将电压确定为第一选择读取电压，并且改变第二读取电压 ，其用于确定存储在存储单元中的数据是否是第三不同电压状态或第四不同电压状态，以及第二不同范围内的电压，并将电压确定为第二选择读取电压。 第一电压状态与第二电压重叠。 第三电压状态与第四电压状态重叠。 第三和第四电压状态的交点处的电压与第二读取电压之间的差异大于第一和第二电压状态与第一读取电压的交点处的电压之间的差。

公开(公告)号：US20170345507A1

公开(公告)日：2017-11-30

申请号：US15680104

申请日：2017-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Chul PARK ,  Seung-Bum KIM ,  Myung-Hoon CHOI

IPC: G11C16/14 ,  G11C16/10 ,  G11C16/34 ,  G11C16/16 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3477

Abstract: A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.