公开(公告)号：US12261220B2

公开(公告)日：2025-03-25

申请号：US18597440

申请日：2024-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woocheol Shin ,  Sunggi Hur ,  Sangwon Baek ,  Junghan Lee

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are stacked in a vertical direction. Each channel extends in a first direction. The gate structure extends in a second direction. The gate structure covers the channels. The source/drain layer is connected to each of opposite sidewalls in the first direction of the channels on the substrate, and includes a doped semiconductor material. The source/drain layer includes first and second epitaxial layers having first and second impurity concentrations, respectively. The first epitaxial layer covers a lower surface and opposite sidewalls in the first direction of the second epitaxial layer. A portion of each of opposite sidewalls in the first direction of the gate structure protrudes in the first direction from opposite sidewalls in the first direction of the channels to partially penetrate through the first epitaxial layer but not to contact the second epitaxial layer.

公开(公告)号：US11387367B2

公开(公告)日：2022-07-12

申请号：US17034421

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woocheol Shin ,  Sunggi Hur ,  Sangwon Baek ,  Junghan Lee

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are stacked in a vertical direction. Each channel extends in a first direction. The gate structure extends in a second direction. The gate structure covers the channels. The source/drain layer is connected to each of opposite sidewalls in the first direction of the channels on the substrate, and includes a doped semiconductor material. The source/drain layer includes first and second epitaxial layers having first and second impurity concentrations, respectively. The first epitaxial layer covers a lower surface and opposite sidewalls in the first direction of the second epitaxial layer. A portion of each of opposite sidewalls in the first direction of the gate structure protrudes in the first direction from opposite sidewalls in the first direction of the channels to partially penetrate through the first epitaxial layer but not to contact the second epitaxial layer.

公开(公告)号：US11961806B2

公开(公告)日：2024-04-16

申请号：US17352503

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Noh Yeong Park ,  Beomjin Park ,  Dong Il Bae ,  Sangwon Baek ,  Hyun-Seung Song

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/562 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including a first region and a second region and a first active pattern on the first region. The first active pattern may include a pair of first source/drain patterns and a first channel pattern therebetween, and the first channel pattern may include a plurality of first semiconductor patterns stacked on the substrate. The semiconductor device may further include a first gate electrode, which is provided on the first channel patterns, and a supporting pattern, which is provided on side surfaces of the plurality of first semiconductor patterns to connect the side surfaces of the plurality of first semiconductor patterns to each other.

公开(公告)号：US11955556B2

公开(公告)日：2024-04-09

申请号：US17836416

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woocheol Shin ,  Sunggi Hur ,  Sangwon Baek ,  Junghan Lee

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are stacked in a vertical direction. Each channel extends in a first direction. The gate structure extends in a second direction. The gate structure covers the channels. The source/drain layer is connected to each of opposite sidewalls in the first direction of the channels on the substrate, and includes a doped semiconductor material. The source/drain layer includes first and second epitaxial layers having first and second impurity concentrations, respectively. The first epitaxial layer covers a lower surface and opposite sidewalls in the first direction of the second epitaxial layer. A portion of each of opposite sidewalls in the first direction of the gate structure protrudes in the first direction from opposite sidewalls in the first direction of the channels to partially penetrate through the first epitaxial layer but not to contact the second epitaxial layer.

公开(公告)号：US20240079466A1

公开(公告)日：2024-03-07

申请号：US18136975

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwon Baek ,  Beomjin Park ,  Myung Gil Kang ,  Dongwon Kim ,  Hyumin Yoo ,  Namkyu Cho

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L2029/42388

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode including, an inner electrode between a first semiconductor pattern of the plurality of semiconductor patterns and a second semiconductor pattern of the plurality of semiconductor patterns, the first semiconductor pattern and the second semiconductor pattern being adjacent to each other, and an outer electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns.