公开(公告)号：US20240130123A1

公开(公告)日：2024-04-18

申请号：US18208459

申请日：2023-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yejin PARK ,  Seung Yoon KIM ,  Heesuk KIM ,  Hyeongjin KIM ,  Sehee JANG ,  Minsoo SHIN ,  Seungjun SHIN ,  Sanghun CHUN ,  Jeehoon HAN ,  Jae-Hwang SIM ,  Jongseon AHN

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06541

Abstract: Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other, a memory channel structure including a first memory portion that penetrates the first gate stack structure, a through contact including a first through portion at a level the same as a level of the first memory portion, and a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion. A minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion.

公开(公告)号：US20220399367A1

公开(公告)日：2022-12-15

申请号：US17681247

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Yoon KIM ,  Sang Hun CHUN ,  Jee Hoon HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11526

Abstract: A semiconductor memory device includes a cell unit including a stack structure and a channel structure penetrating through the stack structure, the stack structure including at least one string selection gate and a plurality of cell gates, cell separation structures separating the cell unit in a first direction, and gate cutting structures defining regions within the cell unit between adjacent cell separation structures. The cell unit includes a first region defined between a first cell separation structure and a first gate cutting structure and a second region defined between the first gate cutting structure and a second gate cutting structure. A ratio of a region of the at least one string selection gate that is occupied by a conductive material in the second region is greater than a ratio of a region of at least one cell gate that is occupied by the conductive material in the second region.

公开(公告)号：US20230186990A1

公开(公告)日：2023-06-15

申请号：US17876694

申请日：2022-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Yoon KIM ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: G11C16/04 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device includes: a stack structure including a ground selection line, first word lines, second word lines, and a string selection line, which are sequentially stacked on a substrate; vertical channel structures penetrating the stack structure and arranged to form a plurality of columns; a lower separation structure crossing a lower portion of the stack structure in a first direction and dividing the ground selection line along a second direction intersecting the first direction; and first and second upper separation structures crossing an upper portion of the stack structure in the first direction and dividing the string selection line along the second direction, wherein the lower separation structure and the first upper separation structure are vertically overlapped with one of the columns of the vertical channel structures, and the second upper separation structures are provided between the vertical channel structures.