公开(公告)号：US09817434B2

公开(公告)日：2017-11-14

申请号：US14989575

申请日：2016-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bo-Geun Kim ,  Kye-Hyun Kyung ,  Jae-Yong Jeong ,  Seung-Hun Choi ,  Seok-Cheon Kwon ,  Chul-Ho Lee

IPC: G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00 ,  G06F1/14 ,  G06F1/32 ,  G06F13/16 ,  G06F1/04 ,  G11C7/22 ,  G06F3/06

CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/14 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0683 ,  G06F13/1689 ,  G11C7/222 ,  Y02D10/14

Abstract: A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.