公开(公告)号：US09536605B2

公开(公告)日：2017-01-03

申请号：US14806780

申请日：2015-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Kook Park ,  Yeong-Taek Lee ,  Dae-Seok Byeon ,  Bo-Geun Kim

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/77

Abstract: Provided are a resistive memory device including a plurality of memory cells, and a method of operating the resistive memory device. The resistive memory device includes a sensing circuit connected to a first signal line, to which a memory cell is connected, the sensing circuit sensing data stored in the memory cell based on a first reference current; and a reference time generator for generating a reference time signal that determines a time point when a result of the sensing is to be output, based on the first reference current.

Abstract translation: 提供了包括多个存储单元的电阻式存储器件以及操作该电阻式存储器件的方法。 电阻式存储器件包括连接到存储单元连接到的第一信号线的感测电路，感测电路基于第一参考电流感测存储在存储器单元中的数据; 以及参考时间发生器，用于产生基于所述第一参考电流确定所述感测的结果的时间点的参考时间信号。

公开(公告)号：US09147483B2

公开(公告)日：2015-09-29

申请号：US14068122

申请日：2013-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jun Yoon ,  Jae-Yong Jeong ,  Myoung-Hoon Choi ,  Bo-Geun Kim ,  Ki-Tae Park

IPC: G11C16/26 ,  G06F11/10 ,  G11C11/56 ,  G11C16/34 ,  G11C29/04

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/3422 ,  G11C2029/0411 ,  G11C2211/5641

Abstract: A memory device useable with a memory system includes a voltage generator to a plurality of first candidate voltages and a plurality of second candidate voltages, and an X decoder to sequentially apply each of the plurality of first candidate voltages and each of the plurality of second candidate voltages to one or more cells of a memory cell array, and then to apply one of the plurality of first candidate voltages and one of the plurality of second candidate voltages as a first read voltage and a second voltage, respectively, to read data from the cells of the memory cell array according to a characteristic of the cells of the memory cell array.

Abstract translation: 可与存储器系统一起使用的存储装置包括电压发生器到多个第一候选电压和多个第二候选电压，以及X解码器，以顺序地施加多个第一候选电压中的每一个，并且多个第二候选 电压到存储单元阵列的一个或多个单元，然后分别施加多个第一候选电压和多个第二候选电压中的一个作为第一读取电压和第二电压以从 根据存储单元阵列的单元的特性，存储单元阵列的单元。

公开(公告)号：US09269429B2

公开(公告)日：2016-02-23

申请号：US14665127

申请日：2015-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Kook Park ,  Dae-Seok Byeon ,  Yeong-Taek Lee ,  Bo-Geun Kim ,  Yong-Kyu Lee ,  Hyo-Jin Kwon

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C5/025 ,  G11C13/0023 ,  G11C13/0033 ,  G11C2213/71

Abstract: A resistive memory device includes a memory cell array including a plurality vertically stacked layers having one layer designated as an interference-free layer and another layer designated as an access prohibited layer, wherein the interference-free layer and the access prohibited layer share a connection with at least one signal line and access operations directed to memory cells the access prohibited layer are prohibited.

Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列包括多个垂直层叠的层，其中一层被指定为无干扰层，另一层指定为禁止访问层，其中无干扰层和禁止访问层共享与 禁止至少一条信号线和针对存储器单元访问禁止层的访问操作。

公开(公告)号：US09817434B2

公开(公告)日：2017-11-14

申请号：US14989575

申请日：2016-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bo-Geun Kim ,  Kye-Hyun Kyung ,  Jae-Yong Jeong ,  Seung-Hun Choi ,  Seok-Cheon Kwon ,  Chul-Ho Lee

IPC: G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00 ,  G06F1/14 ,  G06F1/32 ,  G06F13/16 ,  G06F1/04 ,  G11C7/22 ,  G06F3/06

CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/14 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0683 ,  G06F13/1689 ,  G11C7/222 ,  Y02D10/14

Abstract: A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times.

公开(公告)号：US09177660B2

公开(公告)日：2015-11-03

申请号：US14069588

申请日：2013-11-01

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyun-Jun Yoon ,  Jae-Yong Jeong ,  Myung-Hoon Choi ,  Bo-Geun Kim ,  Ki-Tae Park

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/04 ,  G11C29/00

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G06F11/1072 ,  G11C16/0483 ,  G11C29/00

Abstract: A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.

Abstract translation: 一种操作存储器件的方法包括将确定第一电压状态或第二电压状态的第一读取电压改变为第一范围内的电压并将电压确定为第一选择读取电压，并且改变第二读取电压 ，其用于确定存储在存储单元中的数据是否是第三不同电压状态或第四不同电压状态，以及第二不同范围内的电压，并将电压确定为第二选择读取电压。 第一电压状态与第二电压重叠。 第三电压状态与第四电压状态重叠。 第三和第四电压状态的交点处的电压与第二读取电压之间的差异大于第一和第二电压状态与第一读取电压的交点处的电压之间的差。