公开(公告)号：US20230111057A1

公开(公告)日：2023-04-13

申请号：US17734455

申请日：2022-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Chul LEE ,  Kwang Seok KIM ,  Jeong-Heon PARK

IPC: H01L43/02 ,  H01L43/10

Abstract: A magnetic tunnel junction device includes a pinned magnetic layer, a free magnetic layer, and a tunnel barrier layer between the pinned and free magnetic layers. The free magnetic layer includes a first free layer, a second free layer spaced apart from the tunnel barrier layer with the first free layer therebetween, and a spacer layer between the first free layer and the second free layer. The first free layer and the second free layer are antiferromagnetically coupled to each other by the spacer layer, and each of the first free layer and the second free layer has a magnetization direction substantially perpendicular to an interface between the free magnetic layer and the tunnel barrier layer. A thermal stability of the free magnetic layer is in a range of 0 to 15.

公开(公告)号：US20220123201A1

公开(公告)日：2022-04-21

申请号：US17490353

申请日：2021-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ung Hwan PI ,  Seonggeon PARK ,  Jeong-Heon PARK ,  Sung Chul LEE

IPC: H01L43/02 ,  H01L27/22 ,  H01F10/32

Abstract: A magnetic memory device includes a first magnetic layer extending in a first direction, a pinned layer on the first magnetic layer, and a second magnetic layer vertically overlapping with the pinned layer with the first magnetic layer interposed between the pinned layer and the second magnetic layer. The first magnetic layer includes, a plurality of magnetic domains arranged in the first direction, and at least one magnetic domain wall between the plurality of magnetic domains, and a magnetization direction of the second magnetic layer is substantially parallel to a top surface of the first magnetic layer.

公开(公告)号：US20210367142A1

公开(公告)日：2021-11-25

申请号：US16950009

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Chul LEE ,  Whankyun KIM ,  Joonmyoung LEE ,  Junho JEONG

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/14 ,  G11C11/16 ,  G11C11/18

Abstract: A magnetic memory device including a lower electrode on a substrate; a conductive line on the lower electrode; and a magnetic tunnel junction pattern on the conductive line, wherein the conductive line includes a first conductive line adjacent to the magnetic tunnel junction pattern; a second conductive line between the lower electrode and the first conductive line; and a high resistance layer at least partially between the first conductive line and the second conductive line, a resistivity of the second conductive line is lower than a resistivity of the first conductive line, and a resistivity of the high resistance layer is higher than the resistivity of the first conductive line and higher than the resistivity of the second conductive line.

公开(公告)号：US20190189906A1

公开(公告)日：2019-06-20

申请号：US16028688

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Chul LEE ,  Se Chung OH ,  Sangjun YUN ,  Jae Hoon KIM ,  KyungTae NAM ,  Eunsun NOH

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01L43/10

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic memory device includes a substrate, a tunnel barrier pattern on the substrate, a first magnetic pattern and a second magnetic pattern spaced apart from each other with the tunnel barrier pattern therebetween, and a short preventing pattern spaced apart from the tunnel barrier pattern with the second magnetic pattern therebetween. The short preventing pattern includes at least two oxide layers and at least two metal layers, which are alternately stacked.