公开(公告)号：US08981824B2

公开(公告)日：2015-03-17

申请号：US14201285

申请日：2014-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jin Park ,  Tae Kwang Jang ,  Jenlung Liu

IPC: H03L7/06 ,  H03L7/10

CPC classification number: H03L7/10 ,  H03L7/095 ,  H03L7/0997 ,  H03L2207/50

Abstract: A method of operating a phase-locked loop (PLL) such as an all-digital PLL includes operations of comparing a reference clock signal with a feedback signal of the PLL and outputting a comparison signal according to a result of the comparison, and detecting whether the PLL is in a lock state by using a number of times the comparison signal is toggled.

Abstract translation: 操作诸如全数字PLL的锁相环（PLL）的方法包括将参考时钟信号与PLL的反馈信号进行比较并根据比较结果输出比较信号的操作，以及检测是否 PLL通过使用比较信号切换的次数处于锁定状态。

公开(公告)号：US09618958B2

公开(公告)日：2017-04-11

申请号：US14203797

申请日：2014-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Kwang Jang ,  Jen Lung Liu ,  Nan Xing ,  Jae Jin Park

IPC: G05F3/24 ,  G05F3/26

CPC classification number: G05F3/242 ,  G05F3/26

Abstract: A current generator includes a first current generation circuit configured to generate a first current having a first current noise which depends on a change in a supply voltage, a second current generation circuit configured to generate a second current having a second current noise which depends on the change in the supply voltage, and a current subtracting circuit configured to generate a third current with the first current noise and the second current noise removed by subtracting the second current from the first current.

公开(公告)号：US08981828B2

公开(公告)日：2015-03-17

申请号：US14199139

申请日：2014-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Kwang Jang ,  Jen Lung Liu ,  Nan Xing ,  Jae Jin Park

IPC: H03H11/16 ,  H03K5/15

CPC classification number: H03K5/15 ,  H03K5/1504 ,  H03K5/1508

Abstract: A multi-phase generator includes an oscillator unit including a plurality of first buffer units forming a single closed loop and a delay unit including a plurality of second buffer units respectively connected to a plurality of nodes, wherein each of the plurality of nodes is connected between two adjacent buffer units of the first buffer units. A phase of an output signal of a second buffer unit, among the second buffer units, lags behind a phase of an output signal of a first buffer unit, among the first buffer units.

Abstract translation: 多相发生器包括：振荡器单元，包括形成单个闭环的多个第一缓冲单元和包括分别连接到多个节点的多个第二缓冲单元的延迟单元，其中多个节点中的每一个连接在 第一缓冲单元的两个相邻缓冲单元。 在第一缓冲单元中，第二缓冲单元中的第二缓冲单元的输出信号的相位滞后于第一缓冲单元的输出信号的相位。