公开(公告)号：US20170317213A1

公开(公告)日：2017-11-02

申请号：US15410238

申请日：2017-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mi-Seon PARK ,  Gi-Gwan PARK ,  Tae-Jong LEE ,  Yong-Suk TAK ,  Ki-Yeon PARK

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure directly on a sidewall of the gate structure, and a source/drain layer on a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a silicon oxycarbonitride (SiOCN) pattern and a silicon dioxide (SiO2) pattern sequentially stacked.

公开(公告)号：US20200098918A1

公开(公告)日：2020-03-26

申请号：US16693439

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jong LEE ,  Sanghyuk HONG ,  TaeYong KWON ,  Sunjung KIM ,  Cheol KIM

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L21/8238

Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.

公开(公告)号：US20200373387A1

公开(公告)日：2020-11-26

申请号：US16993514

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han LEE ,  Jae-Hwan LEE ,  Sang-Su KIM ,  Hwan-Wook CHOI ,  Tae-Jong LEE ,  Seung-Mo HA

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US20200091286A1

公开(公告)日：2020-03-19

申请号：US16694031

申请日：2019-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han LEE ,  Jae-Hwan LEE ,  Sang-Su KIM ,  Hwan-Wook CHOI ,  Tae-Jong LEE ,  Seung-Mo HA

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.