公开(公告)号：US20170040323A1

公开(公告)日：2017-02-09

申请号：US15298288

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwan LEE ,  SANGSU KIM

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/165 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/3247 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7842 ,  H01L29/785

Abstract: A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

Abstract translation: 半导体器件可以包括设置在基板上以容纳硅锗的应变松弛缓冲层，设置在应变松弛缓冲层上的半导体图案，以包括源区域，漏极区域和将源极区域与漏极连接的沟道区域 区域，以及包围沟道区并在衬底和沟道区之间延伸的栅电极。 源极和漏极区域可以含有浓度为30at％或更高的锗。

公开(公告)号：US20160343819A1

公开(公告)日：2016-11-24

申请号：US15133424

申请日：2016-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjine PARK ,  Jae-Hwan LEE ,  Yongsun KO

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/42356 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a fin structure on a substrate, device isolation patterns on the substrate at opposite sides of the fin structure, a gate electrode intersecting the fin structure and the device isolation patterns, a gate dielectric pattern between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns, and gate spacers on opposite sidewalls of the gate electrode, wherein, on each of the device isolation patterns, a bottom surface of the gate dielectric pattern is at a higher level than bottom surfaces of the gate spacers.

Abstract translation: 半导体器件包括在衬底上的翅片结构，在鳍结构的相对侧的衬底上的器件隔离图案，与鳍结构相交的栅电极和器件隔离图案，栅电极和鳍结构之间的栅极电介质图案 并且在栅极电极和器件隔离图案之间以及栅极电极的相对侧壁上的栅极间隔物，其中，在每个器件隔离图案上，栅极电介质图案的底表面处于比所述栅极电极的底表面更高的水平 门垫片。

公开(公告)号：US20160112474A1

公开(公告)日：2016-04-21

申请号：US14919291

申请日：2015-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwan LEE

IPC: H04L29/06 ,  G06F3/0484 ,  G06F3/0482

CPC classification number: H04L65/403 ,  H04M1/274508 ,  H04M1/72519 ,  H04M1/72522 ,  H04M2250/64

Abstract: A method of providing a content in an electronic device is provided. The method includes include detecting a mapping event associated with a content of the electronic device, in response to detecting the mapping event, confirming the content, determining a contact point for mapping the content, and mapping the content to the contact point for mapping.

Abstract translation: 提供了一种在电子设备中提供内容的方法。 该方法包括响应于检测到映射事件，确认内容，确定用于映射内容的联系点以及将内容映射到联系人以进行映射来检测与电子设备的内容相关联的映射事件。

公开(公告)号：US20150311286A1

公开(公告)日：2015-10-29

申请号：US14606017

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hwan LEE ,  Sangsu KIM

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/3247 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7842 ,  H01L29/785

Abstract: A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

Abstract translation: 半导体器件可以包括设置在基板上以容纳硅锗的应变松弛缓冲层，设置在应变松弛缓冲层上的半导体图案，以包括源区域，漏极区域和将源极区域与漏极连接的沟道区域 区域，以及包围沟道区并在衬底和沟道区之间延伸的栅电极。 源极和漏极区域可以含有浓度为30at％或更高的锗。

公开(公告)号：US20200373387A1

公开(公告)日：2020-11-26

申请号：US16993514

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han LEE ,  Jae-Hwan LEE ,  Sang-Su KIM ,  Hwan-Wook CHOI ,  Tae-Jong LEE ,  Seung-Mo HA

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US20200091286A1

公开(公告)日：2020-03-19

申请号：US16694031

申请日：2019-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han LEE ,  Jae-Hwan LEE ,  Sang-Su KIM ,  Hwan-Wook CHOI ,  Tae-Jong LEE ,  Seung-Mo HA

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US20150035009A1

公开(公告)日：2015-02-05

申请号：US14336084

申请日：2014-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Jae YANG ,  Sang-Su KIM ,  Jae-Hwan LEE ,  Jung-Dal CHOI

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/06 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.

Abstract translation: 翅片场效应晶体管包括分别从第一和第二鳍结构上的衬底，第一和第二栅电极突出的第一鳍结构和第二鳍结构，以及在第一鳍和第二鳍结构中的每一个之间的栅极介电层 以及第一和第二栅电极。 第一和第二鳍结构中的每一个包括衬底上的缓冲图案，缓冲图案上的沟道图案，以及设置在沟道图案和衬底之间的蚀刻停止图案。 蚀刻停止图案包括具有大于缓冲图案的蚀刻电阻率的蚀刻电阻率的材料。