公开(公告)号：US09082506B2

公开(公告)日：2015-07-14

申请号：US14204444

申请日：2014-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Sik Na

IPC: G11C7/00 ,  G11C5/14 ,  G11C8/00 ,  G11C8/16 ,  G11C11/4076 ,  G11C5/04 ,  G11C7/22 ,  G11C11/4074 ,  G11C8/18

CPC classification number: G11C11/4076 ,  G11C5/04 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2207/2272

Abstract: An operating method of a delay locked loop (DLL) circuit for a semiconductor memory device is disclosed. The DLL circuit may include a plurality of sub-circuits. The method may include calculating an additive latency value based on predetermined parameters, and controlling a set of the plurality of sub-circuits of the DLL circuit to be maintained in a turn-off state based on the calculated additive latency value, during a period of time after the semiconductor device receives an operation command in a power saving mode.

Abstract translation: 公开了一种用于半导体存储器件的延迟锁定环（DLL）电路的操作方法。 DLL电路可以包括多个子电路。 该方法可以包括基于预定参数计算附加延迟值，并且在一段时间内基于所计算的附加延迟值来控制DLL电路的多个子电路的集合将被保持在关断状态 半导体器件在省电模式下接收到操作命令之后的时间。

公开(公告)号：US09077350B2

公开(公告)日：2015-07-07

申请号：US14212362

申请日：2014-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Sik Na ,  In-Dal Song

IPC: H03L7/06 ,  H03L7/081 ,  H03L7/095 ,  G11C7/22

CPC classification number: H03L7/0812 ,  G11C7/222 ,  H03L7/0818 ,  H03L7/095

Abstract: A delay-locked loop circuit includes a phase detector and a coarse-lock detector. The phase detector receives a feedback clock and a first clock to generate first and second phase detecting signals, respectively. The coarse-lock detector generates a coarse-lock signal based on changes of phase of the first and second phase detecting signals.

Abstract translation: 延迟锁定环路电路包括相位检测器和粗略锁定检测器。 相位检测器接收反馈时钟和第一时钟以分别产生第一和第二相位检测信号。 粗锁检测器基于第一和第二相位检测信号的相位变化产生粗锁信号。