公开(公告)号：US09312963B2

公开(公告)日：2016-04-12

申请号：US14552601

申请日：2014-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Kyoum Kim ,  Seok-Hun Hyun ,  In-Dal Song ,  Seong-Jin Jang ,  Jung-Hwan Choi

IPC: H04B10/50 ,  H04B10/80 ,  H04B10/67 ,  H04B10/572 ,  H04J14/00 ,  H04J14/02

CPC classification number: H04B10/572 ,  H04B10/506 ,  H04B10/671 ,  H04B10/801 ,  H04J14/0278

Abstract: An optical transmission converter comprises a wavelength selector configured to output a reception wavelength selection signal and a transmission wavelength selection signal in response to a wavelength control signal, an opto-electrical converter configured to convert a selection optical signal into a reception electrical signal based on a reception optical signal from a host device and the reception wavelength selection signal, and an electro-optical converter configured to convert a transmission electrical signal into a transmission optical signal based on the transmission wavelength selection signal and the transmission electrical signal.

Abstract translation: 一种光传输转换器，包括：波长选择器，被配置为响应于波长控制信号输出接收波长选择信号和传输波长选择信号;光电转换器，被配置为基于选择光信号将选择光信号转换为接收电信号 接收光信号和接收波长选择信号，以及电光转换器，被配置为基于传输波长选择信号和传输电信号将传输电信号转换为传输光信号。

公开(公告)号：US10283186B2

公开(公告)日：2019-05-07

申请号：US15787101

申请日：2017-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-Hwan Jeon ,  Kyung-Soo Ha ,  Jin-Seok Heo ,  In-Dal Song ,  Jung-Hwan Choi

IPC: G11C11/24 ,  G11C11/402 ,  G11C7/22 ,  G11C11/22 ,  G11C7/10 ,  G11C11/4093

Abstract: A data alignment circuit of a semiconductor memory device including: a data sampling circuit configured to receive a data sequence and an internal data strobe signal, wherein the data sampling circuit samples the data sequence based on the internal data strobe signal to generate first and second data sequences; a division circuit configured to receive a clock signal and the internal data strobe signal, divide the clock signal to produce a divided clock signal and output an alignment control signal by sampling the divided clock signal based on the internal data strobe signal; and a data alignment block configured to receive the first and second data sequences, and the alignment control signal, and align the first and second data sequences in parallel to output internal data.

公开(公告)号：US09269412B2

公开(公告)日：2016-02-23

申请号：US14198028

申请日：2014-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Shim ,  In-Dal Song ,  Young Choi

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

Abstract: A memory device is provided. The memory device includes programming first bit data into a plurality of memory cells; identifying target memory cells which are in a first state and whose threshold voltages are equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating a plurality of third bit data by performing a first process on the second bit data; selecting third bit data which changes a largest number of target memory cells from the first state to a second state in response to the memory cells being programmed with each of the plurality of third bit data from the plurality of third bit data; and programming the selected third bit data into the memory cells.

Abstract translation: 提供存储器件。 存储器件包括将第一位数据编程到多个存储器单元中; 识别处于第一状态并且其阈值电压等于或大于来自用第一位数据编程的存储器单元的第一电压的目标存储器单元; 接收要编程到存储器单元中的第二位数据; 通过对所述第二位数据执行第一处理来计算多个第三位数据; 响应于来自多个第三位数据的多个第三位数据中的每一个对存储器单元进行编程，选择将最大数目的目标存储器单元从第一状态改变到第二状态的第三位数据; 并将所选择的第三位数据编程到存储器单元中。

公开(公告)号：US09542343B2

公开(公告)日：2017-01-10

申请号：US14091385

申请日：2013-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Kyoum Kim ,  In-Dal Song ,  Jung-Hwan Choi

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/4022

Abstract: A memory module includes memory devices arranged in ranks and columns and designated in first and second groupings, the first grouping includes memory devices arranged in only a first rank nearest a memory controller and directly connected to the memory controller, the memory devices in the second grouping are indirectly connected to the memory controller via a corresponding memory device in the first grouping arranged in a same column, and each memory device selectively provides either self-data retrieved from a constituent memory core or other-data retrieved from a memory core of another memory device during the read operation.

Abstract translation: 存储器模块包括以列和列排列并且在第一和第二组中指定的存储器件，第一组包括只排列在最靠近存储器控制器并且直接连接到存储器控制器的第一级的存储器件，第二组中的存储器件 经由布置在同一列中的第一组中的相应存储器件间接地连接到存储器控制器，并且每个存储器件选择性地提供从组成存储器核心检索的自身数据或从另一存储器的存储器核心检索的其他数据 读取操作期间的设备。

公开(公告)号：US09077350B2

公开(公告)日：2015-07-07

申请号：US14212362

申请日：2014-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Sik Na ,  In-Dal Song

IPC: H03L7/06 ,  H03L7/081 ,  H03L7/095 ,  G11C7/22

CPC classification number: H03L7/0812 ,  G11C7/222 ,  H03L7/0818 ,  H03L7/095

Abstract: A delay-locked loop circuit includes a phase detector and a coarse-lock detector. The phase detector receives a feedback clock and a first clock to generate first and second phase detecting signals, respectively. The coarse-lock detector generates a coarse-lock signal based on changes of phase of the first and second phase detecting signals.

Abstract translation: 延迟锁定环路电路包括相位检测器和粗略锁定检测器。 相位检测器接收反馈时钟和第一时钟以分别产生第一和第二相位检测信号。 粗锁检测器基于第一和第二相位检测信号的相位变化产生粗锁信号。

公开(公告)号：US09230621B2

公开(公告)日：2016-01-05

申请号：US14197883

申请日：2014-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Shim ,  In-Dal Song

IPC: G06F13/12 ,  G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076

Abstract: A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a buffer that inputs a first signal and outputs a first delay signal, a command decoder that outputs a second signal, a mask pulse signal generator that inputs the first delay signal and the second signal and generates a mask pulse signal, and a signal reshaper that inputs the first delay signal, the second signal and the mask pulse signal and reshapes the first delay signal or the second signal.

Abstract translation: 提供一种半导体存储器件及其操作方法。 半导体存储器件包括输入第一信号并输出​​第一延迟信号的缓冲器，输出第二信号的命令解码器，输入第一延迟信号和第二信号并产生掩模脉冲信号的掩码脉冲信号发生器， 以及输入第一延迟信号，第二信号和掩模脉冲信号并重新形成第一延迟信号或第二信号的信号整形器。

公开(公告)号：US09088287B2

公开(公告)日：2015-07-21

申请号：US14193595

申请日：2014-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hun-Dae Choi ,  In-Dal Song

IPC: H03K23/42 ,  H03K23/66

CPC classification number: H03K23/42 ,  H03K23/667

Abstract: A clock generation device includes a flip-flop, a clock division unit, and a clock comparator. The flip-flop generates a chip selection signal synchronized with an internal clock signal. The clock division unit generates second divided clock signals based on a first divided clock signal. The clock comparator selects ones of the second divided clock signals based on the chip selection signal. The clock division unit divides the internal clock signal based on the first divided clock signal and the selected one of the second divided clock signals.

Abstract translation: 时钟生成装置包括触发器，时钟分割单元和时钟比较器。 触发器产生与内部时钟信号同步的芯片选择信号。 时钟分割单元基于第一分频时钟信号产生第二分频时钟信号。 时钟比较器基于芯片选择信号选择第二分频时钟信号中的一个。 时钟分频单元根据第一分频时钟信号和所选择的第二分频时钟信号中的一个分频内部时钟信号。

公开(公告)号：US20150185812A1

公开(公告)日：2015-07-02

申请号：US14560272

申请日：2014-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hun Hyun ,  Jeong-Kyoum Kim ,  In-Dal Song ,  In-Sung Joe ,  Jung-Hwan Choi ,  Hyun-II Byun ,  Yong-Won Jung

IPC: G06F1/32 ,  G11C11/4074 ,  G11C7/10

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C7/1054 ,  G11C7/1081 ,  Y02D10/14

Abstract: A memory system includes a memory controller and a memory device. The memory device includes a first converter and a first power controller. The memory device is connected to the memory controller through a channel including at least one optical signal line. The first converter converts between at least one optical signal of the at least one optical signal line and at least one internal electrical signal of the memory device. The first power controller controls power consumption of the first converter based on an operating state of the memory device.

Abstract translation: 存储器系统包括存储器控制器和存储器件。 存储器件包括第一转换器和第一功率控制器。 存储器件通过包括至少一个光信号线的通道连接到存储器控制器。 第一转换器在至少一个光信号线的至少一个光信号与存储器件的至少一个内部电信号之间进行转换。 第一功率控制器基于存储器件的操作状态来控制第一转换器的功耗。