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1.发明公开公开(公告)号：US20230141322A1
公开(公告)日：2023-05-11
申请号：US17985193
申请日：2022-11-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juyun Lee , Sunggeun Kim , Hyeonju Lee , Seuk Son , Kangjik Kim , Jaehyun Park
CPC classification number: H03L7/0807 , H03L7/089 , H03L7/093 , H03L7/0998
Abstract: A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.
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Patent Agency Ranking
公开(公告)号：US12068752B2
公开(公告)日：2024-08-20
申请号：US17985193
申请日：2022-11-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juyun Lee , Sunggeun Kim , Hyeonju Lee , Seuk Son , Kangjik Kim , Jaehyun Park
CPC classification number: H03L7/0807 , H03L7/089 , H03L7/093 , H03L7/0998
Abstract: A clock data recovery circuit includes a bang bang phase detector receiving data and a clock signal and determining whether a phase of the clock signal leads or lags a phase of the data, a digital loop filter receiving an output of the bang bang phase detector and filtering input jitter, an accumulator accumulating an output from the digital loop filter, an encoder encoding an output of the accumulator to generate a phase interpolation code, and a phase interpolator configured to generate the clock signal with an output phase in accordance with the phase interpolation code. The digital loop filter comprises a first sigma delta modulation (SDM) arithmetic block circuit connected to the bang bang phase detector.
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公开(公告)号：US11740270B2
公开(公告)日：2023-08-29
申请号：US17943551
申请日：2022-09-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Juyun Lee , Hanseok Kim , Jiyoung Kim , Jaehyun Park , Hyeonju Lee , Kangjik Kim , Sunggeun Kim , Seuk Son , Hobin Song , Nakwon Lee
CPC classification number: G01R25/04 , H03L7/085 , H03L7/0807
Abstract: An apparatus for generating an output signal having a waveform that is repeated every period, includes a storage configured to store values corresponding to the waveform in a portion of a period of the output signal, a counter configured to generate a first index of a sample included in the output signal, a controller configured to generate at least one control signal based on the first index and the period of the output signal, and a calculation circuit configured to generate the output signal by calculating an output from the storage based on the at least one control signal.
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公开(公告)号：US12212645B2
公开(公告)日：2025-01-28
申请号：US18243442
申请日：2023-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juyun Lee , Vishnu Kalyanamahadevi Gopalan Jawarlal , Kang Jik Kim , Hyo Gyuem Rhew , Jae Hyun Park
Abstract: A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.
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5.发明公开公开(公告)号：US20240302432A1
公开(公告)日：2024-09-12
申请号：US18597499
申请日：2024-03-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hobin SONG , Juyun Lee , Jiyoung Kim , Jaehyun Park , Sooeun Lee , Insik Hwang
IPC: G01R31/3183 , G01R31/317 , G01R31/3187 , H03K5/00 , H03K5/13 , H03L7/08 , H03L7/081
CPC classification number: G01R31/318328 , G01R31/31724 , G01R31/3187 , H03K5/13 , H03L7/0807 , H03K2005/00052 , H03L7/0812
Abstract: A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.
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公开(公告)号：US11804945B2
公开(公告)日：2023-10-31
申请号：US17669262
申请日：2022-02-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juyun Lee , Vishnu Kalyanamahadevi Gopalan Jawarlal , Kang Jik Kim , Hyo Gyuem Rhew , Jae Hyun Park
CPC classification number: H04L7/0016 , H03L7/0807
Abstract: A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.
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