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公开(公告)号：US11003449B2
公开(公告)日：2021-05-11
申请号：US16256266
申请日：2019-01-24
发明人： Moo-Kyoung Chung , Woong Seo , Ho-Young Kim , Soo-Jung Ryu , Dong-Hoon Yoo , Jin-Seok Lee , Yeon-Gon Cho , Chang-Moo Kim , Seung-Hun Jin
IPC分类号： G06F9/30
摘要： A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.
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2.发明申请公开(公告)号：US20190197760A1
公开(公告)日：2019-06-27
申请号：US16111608
申请日：2018-08-24
发明人： Yeon-Gon Cho , Woong Seo
摘要： A graphics processing unit (GPU), configured to perform tile-based rendering using prefetched graphics data, includes a tiler configured to perform binning on a current frame and obtain a first binning bitstream of a first tile among a plurality of tiles of the current frame, a binning correlator configured to determine whether the first tile and a second tile of a previous frame are similar to each other by using the first binning bitstream and a second binning bitstream of the second tile, where the second tile has a same tile ID as the first tile, a prefetcher configured to prefetch second graphics data used to render the second tile by using the tile ID, when it is determined that the first tile and the second tile are similar to each other, and at least one processor configured to render the current frame using the prefetched second graphics data.
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公开(公告)号：US09983910B2
公开(公告)日：2018-05-29
申请号：US15146044
申请日：2016-05-04
发明人： Minseok Lee , John Dongjun Kim , Woong Seo , Soojung Ryu , Yeongon Cho
CPC分类号： G06F9/5038 , G06F9/46
摘要： A processor and corresponding method are described including cores having a thread set allocated based on a pre-set implementation order, and a controller configured to receive scheduling information determined based on an implementation pattern regarding the allocated thread set from one of the cores and transmit the scheduling information to another of the cores. The one of cores determines the scheduling information according to characteristics of an application when implementation of the thread set is completed. Each of the cores re-determines an implementation order regarding the allocated thread set based on the determined scheduling information.
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公开(公告)号：US10585709B2
公开(公告)日：2020-03-10
申请号：US14800002
申请日：2015-07-15
发明人： Woong Seo , Yeon-Gon Cho , Soo-Jung Ryu , Seok-Woo Song , John Dongjun Kim , Min-Seok Lee
摘要： An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.
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公开(公告)号：US10388033B2
公开(公告)日：2019-08-20
申请号：US15098786
申请日：2016-04-14
发明人： Yeongon Cho , Seok Kang , Soojung Ryu , Jeongae Park , Woong Seo , Sangheon Lee
摘要： A texture processor includes: a texture cache configured to store textures; a controller configured to determine a texture address corresponding to a requested texture among the stored textures and read a texture corresponding to the texture address from the texture cache; a format converter configured to convert a format of the read texture into another format, based on a degree of texture precision required by a graphics processing unit (GPU); and a texture filter configured to perform texture filtering using the read texture having its format converted into the another format.
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公开(公告)号：US10055810B2
公开(公告)日：2018-08-21
申请号：US15420459
申请日：2017-01-31
发明人： Santosh Abraham , Karthik Ramani , Woong Seo , Kwontaek Kwon , Jeongae Park
CPC分类号： G06T1/60 , G06T15/005 , G06T15/04 , H04N19/426 , H04N19/44 , Y02D10/13
摘要： A texture cache architecture facilitates access of compressed texture data in non-power of two formats, such as the Adaptive Scalable Texture Compression (ASTC) codec. In one implementation, the texture cache architecture includes a controller, a first buffer, a second buffer, and a texture decompressor. A first buffer stores one or more blocks of compressed texel data fetched, in response to a first request, from a first texture cache, where the one or more blocks of compressed texel data including at least requested texel data. The second buffer stores decompressed one or more blocks of compressed texel data and provides the decompressed requested texel data as output to a second texture cache. The one or more blocks of compressed texel data stored by the first buffer includes second texel data in addition to the requested texel data.
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公开(公告)号：US09507753B2
公开(公告)日：2016-11-29
申请号：US14694420
申请日：2015-04-23
发明人： Woong Seo , Han-Joon Kim , John Kim , Soo-Jung Ryu
IPC分类号： G06F15/80 , H04L12/773 , H04L12/721 , G06F15/173 , G06F9/445
CPC分类号： G06F15/80 , G06F9/44505 , G06F15/17312 , H04L45/06 , H04L45/60
摘要： Provided is a processor with a data transfer structure that is excellent in performance and efficiency. According to an aspect, the processor may include a plurality of processing elements, a plurality of routers respectively connected to the processing elements, and a plurality of connection links formed between the routers such that data is transferred between the processors via a network.
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公开(公告)号：US09405349B2
公开(公告)日：2016-08-02
申请号：US14287515
申请日：2014-05-27
发明人： Woong Seo , Yeon-Gon Cho , Soo-Jung Ryu , Seok-Woo Song , John Dongjun Kim , Min-Seok Lee
CPC分类号： G06F1/3234 , G06F1/3287 , G06F1/329 , G06F9/4893 , Y02D10/171 , Y02D10/24
摘要： A multi-core apparatus includes cores each including an active cycle counting unit configured to store an active cycle count, and a stall cycle counting unit configured to store a stall cycle count. The multi-core apparatus further includes a job scheduler configured to determine an optimal number of cores in an active state based on state information received from each of the cores, and adjust power to maintain the optimal number of cores.
摘要翻译： 多核装置包括各自包括被配置为存储活动周期计数的活动周期计数单元的核，以及配置成存储失速循环计数的失速循环计数单元。 多核装置还包括：作业调度器，被配置为基于从每个核接收到的状态信息来确定活动状态的最佳核数，并调整功率以维持最佳核数。
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公开(公告)号：US09042392B2
公开(公告)日：2015-05-26
申请号：US13645800
申请日：2012-10-05
发明人： Woong Seo , Han-Joon Kim , John Kim , Soo-Jung Ryu
IPC分类号： H04L12/28 , H04L12/773 , H04L12/721 , G06F15/173
CPC分类号： G06F15/80 , G06F9/44505 , G06F15/17312 , H04L45/06 , H04L45/60
摘要： Provided is a processor with a data transfer structure that is excellent in performance and efficiency. According to an aspect, the processor may include a plurality of processing elements, a plurality of routers respectively connected to the processing elements, and a plurality of connection links formed between the routers such that data is transferred between the processors via a network.
摘要翻译： 提供了具有优异性能和效率的数据传输结构的处理器。 根据一个方面，处理器可以包括多个处理元件，分别连接到处理元件的多个路由器，以及形成在路由器之间的多个连接链路，使得数据经由网络在处理器之间传送。
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公开(公告)号：US10769837B2
公开(公告)日：2020-09-08
申请号：US16111608
申请日：2018-08-24
发明人： Yeon-Gon Cho , Woong Seo
摘要： A graphics processing unit (GPU), configured to perform tile-based rendering using prefetched graphics data, includes a tiler configured to perform binning on a current frame and obtain a first binning bitstream of a first tile among a plurality of tiles of the current frame, a binning correlator configured to determine whether the first tile and a second tile of a previous frame are similar to each other by using the first binning bitstream and a second binning bitstream of the second tile, where the second tile has a same tile ID as the first tile, a prefetcher configured to prefetch second graphics data used to render the second tile by using the tile ID, when it is determined that the first tile and the second tile are similar to each other, and at least one processor configured to render the current frame using the prefetched second graphics data.
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