公开(公告)号：US20250022504A1

公开(公告)日：2025-01-16

申请号：US18901012

申请日：2024-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOON-JOO EOM ,  SEUNGJUN BAE ,  HYE JUNG KWON ,  YOUNG-JU KIM

IPC: G11C11/4093 ,  G11C5/14 ,  G11C7/02 ,  G11C7/10 ,  G11C7/14 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/50

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

公开(公告)号：US20240071475A1

公开(公告)日：2024-02-29

申请号：US18493051

申请日：2023-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOON-JOO EOM ,  SEUNGJUN BAE ,  HYE JUNG KWON ,  YOUNG-JU KIM

IPC: G11C11/4093 ,  G11C5/14 ,  G11C7/02 ,  G11C7/10 ,  G11C7/14 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/50

CPC classification number: G11C11/4093 ,  G11C5/147 ,  G11C7/02 ,  G11C7/1069 ,  G11C7/14 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C29/028 ,  G11C29/50 ,  G11C29/021 ,  G11C29/023 ,  G11C2207/2254

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

公开(公告)号：US20190164594A1

公开(公告)日：2019-05-30

申请号：US16136895

申请日：2018-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOON-JOO EOM ,  SEUNGJUN BAE ,  HYE JUNG KWON ,  YOUNG-JU KIM

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4074

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

公开(公告)号：US20220093161A1

公开(公告)日：2022-03-24

申请号：US17457077

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOON-JOO EOM ,  SEUNGJUN BAE ,  HYE JUNG KWON ,  YOUNG-JU KIM

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096 ,  G11C7/14 ,  G11C7/20 ,  G11C7/02 ,  G11C29/50 ,  G11C11/4072 ,  G11C29/02 ,  G11C7/10 ,  G11C5/14

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

公开(公告)号：US20190052268A1

公开(公告)日：2019-02-14

申请号：US15922332

申请日：2018-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUN-HA LEE ,  CHANG-KYO LEE ,  YOON-JOO EOM

IPC: H03K19/00 ,  G11C7/10

CPC classification number: H03K19/0005 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/028

Abstract: A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation.

公开(公告)号：US20160164479A1

公开(公告)日：2016-06-09

申请号：US14959195

申请日：2015-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOON-JOO EOM ,  SEUNG-JUN BAE ,  DAE-SIK MOON ,  JOON-YOUNG PARK ,  MIN-SU AHN

IPC: H03F3/45 ,  H03D7/14

CPC classification number: H03D7/1441 ,  H03F3/45183 ,  H03F2203/45051 ,  H03F2203/45466 ,  H03F2203/45674 ,  H03F2203/45702 ,  H03K19/00361

Abstract: A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.

Abstract translation: 缓冲电路包括第一差分放大器，第二差分放大器，第三差分放大器和混频器。 第一差分放大器基于输入信号和参考电压信号产生正差分信号和负差分信号。 第二差分放大器基于正差分信号和负差分信号产生第一信号。 第三差分放大器基于正差分信号和负差分信号产生具有与第一信号不同相位的第二信号。 混频器输出通过混合第一信号和第二信号而产生的信号作为输出信号。

公开(公告)号：US20150036448A1

公开(公告)日：2015-02-05

申请号：US14322129

申请日：2014-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINSU AHN ,  SEUNGJUN BAE ,  JOON-YOUNG PARK ,  YOON-JOO EOM

IPC: G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C7/02 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4093

Abstract: An output circuit includes first and second output drivers. The first output driver is configured to transfer a first data signal directly to an output pad in synchronization with a clock signal. The second output driver is configured to transfer a second data signal directly to the output pad in synchronization with an inversion clock signal. The clock signal and the inversion clock enable multiplexing of the first data signal and the second data signal to provide a multiplexed output data signal.

Abstract translation: 输出电路包括第一和第二输出驱动器。 第一输出驱动器被配置为与时钟信号同步地将第一数据信号直接传送到输出焊盘。 第二输出驱动器被配置为与反相时钟信号同步地将第二数据信号直接传送到输出焊盘。 时钟信号和反相时钟使第一数据信号和第二数据信号复用，从而提供多路输出数据信号。