-
公开(公告)号：US11749337B2
公开(公告)日：2023-09-05
申请号：US17807163
申请日：2022-06-16
发明人： Dae-Sik Moon , Gil-Hoon Cha , Ki-Seok Oh , Chang-Kyo Lee , Yeon-Kyu Choi , Jung-Hwan Choi , Kyung-Soo Ha , Seok-Hun Hyun
IPC分类号： G11C11/40 , G11C11/4076 , G11C11/409 , G06F3/06 , G11C7/22
CPC分类号： G11C11/4076 , G06F3/0604 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G11C7/222 , G11C11/409
摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
-
公开(公告)号：US12020767B2
公开(公告)日：2024-06-25
申请号：US17539761
申请日：2021-12-01
发明人： Dae-Sik Moon , Kyung-Soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
CPC分类号： G11C7/1048 , G11C7/1084 , G11C7/222
摘要： A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
-
公开(公告)号：US11749338B2
公开(公告)日：2023-09-05
申请号：US17816138
申请日：2022-07-29
发明人： Dae-Sik Moon , Gil-Hoon Cha , Ki-Seok Oh , Chang-Kyo Lee , Yeon-Kyu Choi , Jung-Hwan Choi , Kyung-Soo Ha , Seok-Hun Hyun
IPC分类号： G11C11/40 , G11C11/4076 , G11C11/409 , G06F3/06 , G11C7/22
CPC分类号： G11C11/4076 , G06F3/0604 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G11C7/222 , G11C11/409
摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
-
公开(公告)号：US11328078B2
公开(公告)日：2022-05-10
申请号：US16464218
申请日：2017-11-22
发明人： Yeon-Kyu Choi
摘要： Various embodiments of the disclosure provide an apparatus for protecting information. According to various embodiments of the disclosure, an apparatus for monitoring a database includes a transceiver, and a processor operatively coupled to the transceiver. The processor may be configured to acquire a query used in access of the database from the database through the transceiver, replace a first code, included in the acquired query, for query checking to a predefined text, convert the text to a second code for query checking, and output information on validity of the acquired query on the basis of a comparison result of the first code and the second code.
-
5.发明申请公开(公告)号：US20190304517A1
公开(公告)日：2019-10-03
申请号：US16363077
申请日：2019-03-25
发明人： Dae-Sik Moon , Kyung-soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
摘要： A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
-
公开(公告)号：US20190237127A1
公开(公告)日：2019-08-01
申请号：US16230185
申请日：2018-12-21
发明人： DAE-SIK MOON , Gil-Hoon Cha , Ki-Seok Oh , Chang-Kyo Lee , Yeon-Kyu Choi , Jung-Hwan Choi , Kyung-Soo Ha , Seok-Hun Hyun
IPC分类号： G11C11/4076 , G11C11/409 , G06F3/06
CPC分类号： G11C11/4076 , G06F3/0604 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G11C7/222 , G11C11/409
摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
-
公开(公告)号：US12106794B2
公开(公告)日：2024-10-01
申请号：US18330527
申请日：2023-06-07
发明人： Dae-Sik Moon , Gil-Hoon Cha , Ki-Seok Oh , Chang-Kyo Lee , Yeon-Kyu Choi , Jung-Hwan Choi , Kyung-Soo Ha , Seok-Hun Hyun
IPC分类号： G11C11/40 , G06F3/06 , G11C7/22 , G11C11/4076 , G11C11/409
CPC分类号： G11C11/4076 , G06F3/0604 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G11C7/222 , G11C11/409
摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
-
公开(公告)号：US10885950B2
公开(公告)日：2021-01-05
申请号：US16363077
申请日：2019-03-25
发明人： Dae-Sik Moon , Kyung-Soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
摘要： A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
-
公开(公告)号：US10795720B2
公开(公告)日：2020-10-06
申请号：US16073446
申请日：2017-01-26
发明人： Yeon-Kyu Choi
摘要： An electronic device according to an embodiment of the present invention comprises: a memory for storing a list including information related to the termination of one or more first applications of a plurality of applications included in the electronic device; and a processor, wherein the processor executes one or more second applications of the plurality of applications, checks contextual information associated with the electronic device, and, if the contextual information satisfies a specified condition, determines whether to terminate at least one executed application of the one or more executed second applications.
-
公开(公告)号：US12033686B2
公开(公告)日：2024-07-09
申请号：US18314243
申请日：2023-05-09
发明人： Dae-Sik Moon , Gil-Hoon Cha , Ki-Seok Oh , Chang-Kyo Lee , Yeon-Kyu Choi , Jung-Hwan Choi , Kyung-Soo Ha , Seok-Hun Hyun
IPC分类号： G11C11/4076 , G06F3/06 , G11C7/22 , G11C11/409
CPC分类号： G11C11/4076 , G06F3/0604 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G11C7/222 , G11C11/409
摘要： A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.015 秒)
