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Patent Agency Ranking
公开(公告)号：US12063044B2
公开(公告)日：2024-08-13
申请号：US18189599
申请日：2023-03-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsun Lee , Jaewoo Park , Myoungbo Park , Jinook Jung , Junghwan Choi
CPC classification number: H03L7/093 , H03L7/0818 , H03L7/0991
Abstract: A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.
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公开(公告)号：US20240364351A1
公开(公告)日：2024-10-31
申请号：US18765582
申请日：2024-07-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsun Lee , Jaewoo Park , Myoungbo Kwak , Jinook Jung , Junghwan Choi
CPC classification number: H03L7/093 , H03L7/0818 , H03L7/0991
Abstract: A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.
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公开(公告)号：US11201626B1
公开(公告)日：2021-12-14
申请号：US17240570
申请日：2021-04-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Woochul Jung , Yongsun Lee
Abstract: A phase locked loop device may include: a frequency modulating circuit configured to output a reference signal obtained by multiplying a frequency of an input signal by a predetermined ratio based on the input signal; a sigma-delta modulator configured to output division ratio information on one of a plurality of division rates at a number of times proportional to a frequency of the reference signal; and a phase locked loop (PLL) circuit configured to determine whether to activate based on a command signal, and, when activated, perform a phase-locking operation based on a fractional division based on the reference signal and the division ratio information.
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公开(公告)号：US20250167790A1
公开(公告)日：2025-05-22
申请号：US18889081
申请日：2024-09-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yongsun Lee , Suneui Park , Jaewoo Park , Jinook Jung , Myoungbo Kwak
Abstract: An example apparatus for generating a clock includes a phase locked loop circuit to generate a first clock signal having a specified frequency through an oscillator, a monitoring circuit to monitor a first bit error rate (BER) of a first signal received in response to the first clock signal, and a control logic circuit to control the phase locked loop circuit based on a monitoring result. The control logic circuit is to connect a first boosting current source, which is included in the phase locked loop circuit, with the oscillator, when the first bit error rate is equal to or greater than a preset threshold value, and disconnect a second boosting current source, which is previously connected with the oscillator, from the oscillator, when the first bit error rate is less than the threshold value.
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公开(公告)号：US20240056084A1
公开(公告)日：2024-02-15
申请号：US18189599
申请日：2023-03-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsun Lee , Jaewoo Park , Myoungbo Kwak , Jinook Jung , Junghwan Choi
CPC classification number: H03L7/093 , H03L7/0991 , H03L7/0818
Abstract: A digital phase-locked loop (PLL) includes: (i) a digitally controlled oscillator (DCO) configured to generate an oscillation signal having a frequency that is adjustable in response to a frequency control signal, (ii) a divider configured to generate a feedback signal in response to dividing a frequency of the oscillation signal, (iii) a time-to-digital converter (TDC) configured to detect a phase difference between a reference signal and the feedback signal, and generate an error signal having a value that is a function of the phase difference, and (iv) a digital loop filter configured to generate the frequency control signal in response to the error signal and the oscillation signal.
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