公开(公告)号：US11693386B2

公开(公告)日：2023-07-04

申请号：US16992919

申请日：2020-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Kim ,  Kanghyun Baek ,  Kwanghee Lee ,  Yongwoo Jeon ,  Uihui Kwon ,  Yoonsuk Kim

IPC: G05B19/4097 ,  G06N20/00

CPC classification number: G05B19/4097 ,  G06N20/00 ,  G05B2219/45031

Abstract: A method of guiding a semiconductor manufacturing process includes receiving semiconductor manufacturing process data corresponding to a target semiconductor product, generating first semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a technology computer-aided design (TCAD) model trained through machine learning based on training data including TCAD simulation data, generating second semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a compact model generated based on information of measurement of at least one semiconductor characteristic of a first semiconductor product, generating, based on the first semiconductor characteristic data and the second semiconductor characteristic data, a plurality of process policies respectively corresponding to a plurality of strategic references, by using a plurality of strategy models; and providing a final process policy corresponding to the target semiconductor product based on the plurality of process policies.

公开(公告)号：US20240096960A1

公开(公告)日：2024-03-21

申请号：US18239248

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghyun SONG ,  Minsuk Kim ,  Pilkwang Kim ,  Takeshi Okagaki ,  Geunmyeong Kim ,  Ahyoung kim ,  Yoonsuk Kim

IPC: H01L29/08 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a back side interconnection structure extending in a first horizontal direction. An active substrate includes a fin-type active area extending in the first horizontal direction on the back side interconnection structure. A metal silicide film is between the back side interconnection structure and the active substrate. A plurality of gate structures extends in a second horizontal direction perpendicular to the first horizontal direction on the active substrate. A first source/drain area and a second source/drain area are spaced apart from each other in the first horizontal direction with the plurality of gate structures therebetween on the active substrate. The first source/drain area directly contacts the active substrate. The second source/drain area is spaced apart from the active substrate and insulated from the active substrate.

公开(公告)号：US20210063999A1

公开(公告)日：2021-03-04

申请号：US16992919

申请日：2020-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho KIM ,  Kanghyun Baek ,  Kwanghee LEE ,  Yongwoo Jeon ,  Uihui KWON ,  Yoonsuk Kim

IPC: G05B19/4097 ,  G06N20/00

Abstract: A method of guiding a semiconductor manufacturing process includes receiving semiconductor manufacturing process data corresponding to a target semiconductor product, generating first semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a technology computer-aided design (TCAD) model trained through machine learning based on training data including TCAD simulation data, generating second semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a compact model generated based on information of measurement of at least one semiconductor characteristic of a first semiconductor product, generating, based on the first semiconductor characteristic data and the second semiconductor characteristic data, a plurality of process policies respectively corresponding to a plurality of strategic references, by using a plurality of strategy models; and providing a final process policy corresponding to the target semiconductor product based on the plurality of process policies.