公开(公告)号：US20210313439A1

公开(公告)日：2021-10-07

申请号：US17119337

申请日：2020-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee LEE ,  Sangwook KIM ,  Seunggeol NAM ,  Taehwan MOON ,  Yunseong LEE ,  Sanghyun JO ,  Jinseong HEO

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: Disclosed herein is an electronic device including: a lower gate electrode; a ferroelectric layer covering the lower gate electrode; a first insertion layer covering the ferroelectric layer and including a dielectric material; a channel layer provided on the first insertion layer, at a position corresponding to the lower gate electrode, the channel layer including an oxide semiconductor material; and a source electrode and a drain electrode formed to be electrically connected to both ends of the channel layer, respectively.

公开(公告)号：US20210063999A1

公开(公告)日：2021-03-04

申请号：US16992919

申请日：2020-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho KIM ,  Kanghyun Baek ,  Kwanghee LEE ,  Yongwoo Jeon ,  Uihui KWON ,  Yoonsuk Kim

IPC: G05B19/4097 ,  G06N20/00

Abstract: A method of guiding a semiconductor manufacturing process includes receiving semiconductor manufacturing process data corresponding to a target semiconductor product, generating first semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a technology computer-aided design (TCAD) model trained through machine learning based on training data including TCAD simulation data, generating second semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a compact model generated based on information of measurement of at least one semiconductor characteristic of a first semiconductor product, generating, based on the first semiconductor characteristic data and the second semiconductor characteristic data, a plurality of process policies respectively corresponding to a plurality of strategic references, by using a plurality of strategy models; and providing a final process policy corresponding to the target semiconductor product based on the plurality of process policies.

公开(公告)号：US20240120403A1

公开(公告)日：2024-04-11

申请号：US18481444

申请日：2023-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeeun YANG ,  Sangwook KIM ,  Euntae KIM ,  Kwanghee LEE ,  Moonil JUNG

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/443 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/45 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/443 ,  H01L29/66969 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a lower electrode on a substrate, a metal oxide on the lower electrode, a buffer on the metal oxide, an oxide channel in the buffer, a gate insulating layer in the oxide channel, a gate electrode in the gate insulating layer, and an upper electrode on the gate electrode, and the buffer may include a silicide material.

公开(公告)号：US20220384656A1

公开(公告)日：2022-12-01

申请号：US17540607

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee LEE ,  Sangwook KIM

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

公开(公告)号：US20220173099A1

公开(公告)日：2022-06-02

申请号：US17491841

申请日：2021-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook KIM ,  Seunggeol NAM ,  Taehwan MOON ,  Kwanghee LEE ,  Jinseong HEO ,  Hagyoul BAE ,  Yunseong LEE

IPC: H01L27/092 ,  H01L27/11 ,  H01L29/24 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

Abstract: Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

公开(公告)号：US20250072055A1

公开(公告)日：2025-02-27

申请号：US18944685

申请日：2024-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee LEE ,  Sangwook KIM

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

公开(公告)号：US20240222515A1

公开(公告)日：2024-07-04

申请号：US18398912

申请日：2023-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeeun YANG ,  Yongsung KIM ,  Sangwook KIM ,  Kwanghee LEE ,  Moonil JUNG

IPC: H01L29/786 ,  H01L29/423 ,  H10B10/00

CPC classification number: H01L29/7869 ,  H01L29/42392 ,  H10B10/12

Abstract: Provided are a semiconductor device including an oxide semiconductor layer and an electronic device including the semiconductor device. The semiconductor device includes a substrate, a first electrode provided on the substrate, a second electrode provided on the first electrode, an oxide semiconductor layer provided between the first electrode and the second electrode, a gate electrode provided in a thickness direction of the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, wherein a measurement density relative to a theoretical density of the oxide semiconductor layer is about 90% or more. The oxide semiconductor layer of the semiconductor device may have a more uniform and improved film density, and may improve the reliability of the device due to the improved film density.

公开(公告)号：US20240162350A1

公开(公告)日：2024-05-16

申请号：US18496353

申请日：2023-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moonil JUNG ,  Sangwook KIM ,  Euntae KIM ,  Jeeeun YANG ,  Kwanghee LEE ,  Youngkwan CHA

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/1054 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: Semiconductor devices and manufacturing methods thereof are provided. A semiconductor device includes a substrate, a lower electrode on the substrate, an oxide channel on the lower electrode, the oxide channel including vertical extension portions extending in a first direction perpendicular to the substrate, an upper electrode on the oxide channel, a gate insulator on a portion the oxide channel that is exposed by the lower electrode and the upper electrode, and a gate electrode on the gate insulator, wherein the upper electrode and the lower electrode are separated from each other by the oxide channel in the first direction, and the oxide channel is doped with ions.

公开(公告)号：US20240079468A1

公开(公告)日：2024-03-07

申请号：US18457803

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moonil JUNG ,  Sangwook KIM ,  Euntae KIM ,  Jeeeun YANG ,  Kwanghee LEE

IPC: H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/45 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78642 ,  H01L29/7869 ,  H01L21/02491 ,  H01L29/78696

Abstract: Provided are a vertical transistor and a method of manufacturing the same. The vertical transistor includes a substrate, a lower electrode on the substrate and including a metal material, a carbon thin film being conductive and on the lower electrode, an oxide semiconductor layer on the carbon thin film, a gate electrode apart from the oxide semiconductor layer, a gate insulating layer arranged between the oxide semiconductor layer and the gate electrode, and an upper electrode on the oxide semiconductor layer, wherein the lower electrode. The carbon thin film, the oxide semiconductor layer, and the upper electrode are arranged in a direction perpendicular to the substrate.

公开(公告)号：US20230051857A1

公开(公告)日：2023-02-16

申请号：US17540662

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee LEE ,  Sangwook KIM ,  Euntae KIM ,  Jeeeun YANG ,  Moonil JUNG ,  Sangjun HONG

IPC: H01L29/786 ,  H01L29/417

Abstract: Provided are oxide semiconductor transistors. The oxide semiconductor transistor includes a substrate, a channel layer arranged on the substrate and having a flat plate shape extending along one plane, a gate electrode facing a part of the channel layer, and a source region and a drain region separated from each other with the gate electrode therebetween, wherein the source region contacts three or more surfaces of the channel layer, and the drain region contacts three or more surfaces of the channel layer.