公开(公告)号：US20250167113A1

公开(公告)日：2025-05-22

申请号：US18754295

申请日：2024-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeewoong KIM ,  Jinkyu KIM ,  Yunsuk NAM ,  Yoonbeom PARK ,  Keunhwi CHO

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is an integrated circuit device including first and second power lines each overlapping a first cell region, an inter-cell separation region, and a second cell region on a substrate in a vertical direction to the substrate, a first power tap cell penetrating through the substrate and receiving a first voltage from the first power line, a second power tap cell penetrating through the substrate and receiving, from the second power line, a second voltage different from the first voltage, and a dummy gate insulating bridge including first and second dummy gate insulating lines, which are apart from each other with the first and second power tap cells therebetween, and defining a vacuum space, and connected to the first and second dummy gate insulating lines.

公开(公告)号：US20240006522A1

公开(公告)日：2024-01-04

申请号：US18204449

申请日：2023-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junbeom PARK ,  Sangwon BAEK ,  Yunsuk NAM

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66439

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate; a plurality of channel layers on the active region and spaced apart from each other in a vertical direction that is perpendicular to the first direction; a gate structure on the substrate, the gate structure intersecting the active region and the plurality of channel layers, extending in a second direction crossing the first direction, and respectively surrounding the plurality of channel layers; inner spacer layers on both sides of the gate structure in the first direction, and on respective lower surfaces of the plurality of channel layers; a protective layer in contact with the inner spacer layers, the plurality of channel layers, and the active region; and a source/drain region on the active region, on at least one side of the gate structure, and in contact with the inner spacer layers.

公开(公告)号：US20250126860A1

公开(公告)日：2025-04-17

申请号：US18738594

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyun AHN ,  Jinkyu KIM ,  Hidenobu FUKUTOME ,  Jeewoong KIM ,  Yunsuk NAM

IPC: H01L29/08 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes: a substrate including a first surface and a second surface; a fin-type active area extending on the first surface of the substrate in a first horizontal direction, and including a first area and a second area that are adjacent to each other; a first source/drain area arranged on the first area of the fin-type active area; a second source/drain area arranged on the second area of the fin-type active area; and a first filling insulating layer extending between the first source/drain area and the second source/drain area, wherein the first area includes a first conductivity type, wherein the second area includes a second conductivity type that is different from the first conductivity type, and wherein a boundary between the first area and the second area includes a portion that is substantially perpendicular to the first horizontal direction, and overlaps the filling insulating layer.

公开(公告)号：US20240332358A1

公开(公告)日：2024-10-03

申请号：US18380711

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin CHA ,  Jinkyu KIM ,  Yunsuk NAM

IPC: H01L29/06 ,  H01L23/48 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L23/481 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes: a first substrate that includes a first region and a second region; an active pattern disposed on the first region; a source/drain pattern disposed on the active pattern; a through contact disposed on the second region; a first metal layer disposed on the through contact; a second substrate disposed on the first metal layer, wherein the second substrate includes an impurity region; a lower bonding pad disposed between the first metal layer and the second substrate; an upper bonding pad disposed on the lower bonding pad; and a power delivery network layer disposed on a bottom surface of the first substrate, wherein the lower bonding pad and the upper bonding pad are in contact with each other, wherein the through contact is connected to the lower bonding pad, and wherein the impurity region is connected to the upper bonding pad.