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公开(公告)号:US20240237324A9
公开(公告)日:2024-07-11
申请号:US18197428
申请日:2023-05-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeewoong KIM
IPC: H10B10/00 , H01L23/48 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/786
CPC classification number: H10B10/125 , H01L23/481 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/78696
Abstract: A semiconductor memory device includes a substrate including first and second surfaces opposite to each other, a first active pattern on the first surface, a first channel pattern on the first active pattern and a first source/drain pattern connected to the first channel pattern, a gate electrode provided on the first channel pattern and extending in a first direction, the gate electrode adjacent to the first source/drain pattern in a second direction intersecting the first direction, a shared contact provided under the first source/drain pattern and the gate electrode and electrically connecting the first source/drain pattern and the gate electrode to each other, and a backside metal layer on the second surface.
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公开(公告)号:US20240162311A1
公开(公告)日:2024-05-16
申请号:US18225777
申请日:2023-07-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Darong OH , Ho-Jun KIM , Jeewoong KIM
IPC: H01L29/417 , H01L23/48 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC classification number: H01L29/41733 , H01L23/481 , H01L29/0673 , H01L29/42392 , H01L29/6656 , H01L29/775 , H01L29/78696
Abstract: A semiconductor device comprising a substrate including an active pattern, a channel pattern and a source/drain pattern that are on the active pattern, the source/drain pattern connected to the channel pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, an upper contact being adjacent to the active contact and extending into the substrate, a lower power interconnection line buried in the substrate, and a power delivery network layer on a bottom surface of the substrate, wherein the lower power interconnection line includes a connection portion connected to the upper contact, and a lower portion of the upper contact protrudes into the connection portion.
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公开(公告)号:US20240138136A1
公开(公告)日:2024-04-25
申请号:US18197428
申请日:2023-05-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeewoong KIM
IPC: H10B10/00 , H01L23/48 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/786
CPC classification number: H10B10/125 , H01L23/481 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/78696
Abstract: A semiconductor memory device includes a substrate including first and second surfaces opposite to each other, a first active pattern on the first surface, a first channel pattern on the first active pattern and a first source/drain pattern connected to the first channel pattern, a gate electrode provided on the first channel pattern and extending in a first direction, the gate electrode adjacent to the first source/drain pattern in a second direction intersecting the first direction, a shared contact provided under the first source/drain pattern and the gate electrode and electrically connecting the first source/drain pattern and the gate electrode to each other, and a backside metal layer on the second surface.
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公开(公告)号:US20250167113A1
公开(公告)日:2025-05-22
申请号:US18754295
申请日:2024-06-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jeewoong KIM , Jinkyu KIM , Yunsuk NAM , Yoonbeom PARK , Keunhwi CHO
IPC: H01L23/528 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: Provided is an integrated circuit device including first and second power lines each overlapping a first cell region, an inter-cell separation region, and a second cell region on a substrate in a vertical direction to the substrate, a first power tap cell penetrating through the substrate and receiving a first voltage from the first power line, a second power tap cell penetrating through the substrate and receiving, from the second power line, a second voltage different from the first voltage, and a dummy gate insulating bridge including first and second dummy gate insulating lines, which are apart from each other with the first and second power tap cells therebetween, and defining a vacuum space, and connected to the first and second dummy gate insulating lines.
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公开(公告)号:US20240088015A1
公开(公告)日:2024-03-14
申请号:US18462049
申请日:2023-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeewoong KIM , Hojun KIM , Sungmoon LEE , Seungmin CHA
IPC: H01L23/522 , H01L23/528 , H01L23/58
CPC classification number: H01L23/5223 , H01L23/5286 , H01L23/585
Abstract: An integrated circuit device comprising: a dielectric layer; a first power delivery network layer on a first surface of the dielectric layer; a second power delivery network layer on a second surface of the dielectric layer, wherein the second surface is opposite to the first surface in a vertical direction; and a via capacitor between the first surface and the second surface of the dielectric layer, wherein the via capacitor includes a first via electrode structure and a second via electrode structure that are spaced apart from each other in one of a first horizontal direction and a second horizontal direction that intersects with the first horizontal direction, and a first end portion and a second end portion that is opposite to the first end portion of the via capacitor are electrically connected to the first power delivery network layer and the second power delivery network layer, respectively.
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公开(公告)号:US20250142945A1
公开(公告)日:2025-05-01
申请号:US18634355
申请日:2024-04-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sora YOU , Dongyun LEE , Seungmin CHA , Jeewoong KIM
IPC: H01L27/06 , H01L23/528 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/861
Abstract: A semiconductor device may include a diode pattern including a first conductive region and a second conductive region having opposite conductivity types to each other on a base insulating layer, an insulating layer covering the diode pattern on the base insulating layer, a wiring portion on the insulating layer; and a through connector extending through the insulating layer at a periphery of the diode pattern to electrically connect the diode pattern and the wiring portion.
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公开(公告)号:US20230289058A1
公开(公告)日:2023-09-14
申请号:US18198372
申请日:2023-05-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sangho PARK , Kwangyoun KIM , Sooam KIM , Jeewoong KIM , Joonjae PARK , Dockjo YANG , Soonbae YANG , Soyong LEE , Boeun JANG , Youngwoong JOO
IPC: G06F3/04886 , G06F3/044 , G06F3/16 , G06F3/04817
CPC classification number: G06F3/04886 , G06F3/044 , G06F3/167 , G06F3/04817 , H05B6/6435
Abstract: An electronic device comprises: a panel; a sensor configured to detect a user's touch with respect to at least one region among a plurality of areas in the panel; a plurality of icon members positionable to an upper portion of the at least one region from among the plurality of regions of the panel based on the user's touch on the at least one region being detected by the sensor, the plurality of icon members being configured to respectively display icons corresponding to functions performable by the electronic device; and a processor configured to perform a function corresponding to an icon member based on the user's touch on the at least one region detected by the sensor occuring in association with the icon member.
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公开(公告)号:US20250126860A1
公开(公告)日:2025-04-17
申请号:US18738594
申请日:2024-06-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaehyun AHN , Jinkyu KIM , Hidenobu FUKUTOME , Jeewoong KIM , Yunsuk NAM
IPC: H01L29/08 , H01L23/528 , H01L27/088 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/775 , H01L29/786
Abstract: An integrated circuit device includes: a substrate including a first surface and a second surface; a fin-type active area extending on the first surface of the substrate in a first horizontal direction, and including a first area and a second area that are adjacent to each other; a first source/drain area arranged on the first area of the fin-type active area; a second source/drain area arranged on the second area of the fin-type active area; and a first filling insulating layer extending between the first source/drain area and the second source/drain area, wherein the first area includes a first conductivity type, wherein the second area includes a second conductivity type that is different from the first conductivity type, and wherein a boundary between the first area and the second area includes a portion that is substantially perpendicular to the first horizontal direction, and overlaps the filling insulating layer.
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公开(公告)号:US20240413204A1
公开(公告)日:2024-12-12
申请号:US18615708
申请日:2024-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeewoong KIM , Hidenobu Fukutome , Jinkyu Kim , Yunsuk Nam , Dongyun Lee
IPC: H01L29/06 , H01L29/417 , H01L29/423 , H01L29/775 , H01L29/786
Abstract: A semiconductor device includes: insulating patterns spaced apart from each other in a first direction and in a second direction that intersects the first direction; a substrate insulating layer on first side surfaces of the insulating patterns; a device isolation layer on second side surfaces of the insulating patterns; channel layers on the insulating patterns and spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the device isolation layer; gate structures vertically overlapping the insulating patterns, surrounding each of the channel layers, and extending in the second direction; source/drain regions provided outside the gate structures; and backside contact structures electrically connected to the source/drain regions and provided below the source/drain regions, wherein the insulating patterns include protrusions protruding in the vertical direction from an upper surface of the device isolation layer, and, in a region in which the insulating patterns vertically overlap the gate structures, a vertical distance between a lower surface of a lowermost channel layer among the channel layers and an upper surface of the protrusions is greater than a vertical distance between the channel layers.
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