INTEGRATED CIRCUIT DEVICE
    4.
    发明申请

    公开(公告)号:US20250167113A1

    公开(公告)日:2025-05-22

    申请号:US18754295

    申请日:2024-06-26

    Abstract: Provided is an integrated circuit device including first and second power lines each overlapping a first cell region, an inter-cell separation region, and a second cell region on a substrate in a vertical direction to the substrate, a first power tap cell penetrating through the substrate and receiving a first voltage from the first power line, a second power tap cell penetrating through the substrate and receiving, from the second power line, a second voltage different from the first voltage, and a dummy gate insulating bridge including first and second dummy gate insulating lines, which are apart from each other with the first and second power tap cells therebetween, and defining a vacuum space, and connected to the first and second dummy gate insulating lines.

    INTEGRATED CIRCUIT DEVICES INCLUDING VIA CAPACITORS

    公开(公告)号:US20240088015A1

    公开(公告)日:2024-03-14

    申请号:US18462049

    申请日:2023-09-06

    CPC classification number: H01L23/5223 H01L23/5286 H01L23/585

    Abstract: An integrated circuit device comprising: a dielectric layer; a first power delivery network layer on a first surface of the dielectric layer; a second power delivery network layer on a second surface of the dielectric layer, wherein the second surface is opposite to the first surface in a vertical direction; and a via capacitor between the first surface and the second surface of the dielectric layer, wherein the via capacitor includes a first via electrode structure and a second via electrode structure that are spaced apart from each other in one of a first horizontal direction and a second horizontal direction that intersects with the first horizontal direction, and a first end portion and a second end portion that is opposite to the first end portion of the via capacitor are electrically connected to the first power delivery network layer and the second power delivery network layer, respectively.

    INTEGRATED CIRCUIT DEVICE
    8.
    发明申请

    公开(公告)号:US20250126860A1

    公开(公告)日:2025-04-17

    申请号:US18738594

    申请日:2024-06-10

    Abstract: An integrated circuit device includes: a substrate including a first surface and a second surface; a fin-type active area extending on the first surface of the substrate in a first horizontal direction, and including a first area and a second area that are adjacent to each other; a first source/drain area arranged on the first area of the fin-type active area; a second source/drain area arranged on the second area of the fin-type active area; and a first filling insulating layer extending between the first source/drain area and the second source/drain area, wherein the first area includes a first conductivity type, wherein the second area includes a second conductivity type that is different from the first conductivity type, and wherein a boundary between the first area and the second area includes a portion that is substantially perpendicular to the first horizontal direction, and overlaps the filling insulating layer.

    SEMICONDUCTOR DEVICES
    9.
    发明申请

    公开(公告)号:US20240413204A1

    公开(公告)日:2024-12-12

    申请号:US18615708

    申请日:2024-03-25

    Abstract: A semiconductor device includes: insulating patterns spaced apart from each other in a first direction and in a second direction that intersects the first direction; a substrate insulating layer on first side surfaces of the insulating patterns; a device isolation layer on second side surfaces of the insulating patterns; channel layers on the insulating patterns and spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the device isolation layer; gate structures vertically overlapping the insulating patterns, surrounding each of the channel layers, and extending in the second direction; source/drain regions provided outside the gate structures; and backside contact structures electrically connected to the source/drain regions and provided below the source/drain regions, wherein the insulating patterns include protrusions protruding in the vertical direction from an upper surface of the device isolation layer, and, in a region in which the insulating patterns vertically overlap the gate structures, a vertical distance between a lower surface of a lowermost channel layer among the channel layers and an upper surface of the protrusions is greater than a vertical distance between the channel layers.

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