Modular non-volatile flash memory blade

    公开(公告)号:US10466923B2

    公开(公告)日:2019-11-05

    申请号:US14918554

    申请日:2015-10-20

    Abstract: Embodiments of the inventive concept include Open Cloud Server (OCS)-compliant and other enterprise servers having high-density modular non-volatile flash memory blades and associated multi-card modules. A modular non-volatile flash memory blade can be seated within a 1 U tray. The flash memory blade can include a server motherboard and multiple non-volatile flash memory blade multi-card modules. Each of the multi-card modules can include a printed circuit board, a switch coupled to the printed circuit board, a module power port, an input/output port, and riser card slots to receive solid state drive riser cards. The solid state drive riser cards can be seated within a corresponding riser card slot of the multi-card modules, and can each include multiple solid state drive chips. The server motherboard can communicate with the solid state drive chips via the cable connector riser cards and associated cables. The switch can expand each upstream port to multiple downstream ports associate with the solid state drive chips.

    Scalable and configurable non-volatile memory module array

    公开(公告)号:US09841904B2

    公开(公告)日:2017-12-12

    申请号:US14809165

    申请日:2015-07-24

    Inventor: Zhan Ping

    CPC classification number: G06F3/061 G06F3/0655 G06F3/0688 G06F13/4022

    Abstract: Embodiments of the inventive concept include a non-volatile memory module array system. The system can include non-volatile memory modules each including a first port, a second port, solid state drives, a switch, and a port configuration logic section. The system can include a bus connected to the first or second ports. The system can include a host to communicate with the non-volatile memory modules via the bus. The port configuration logic section can toggle between a first port configuration associated with the second port and a second port configuration associated with the second port. The port configuration logic section can include a first non-volatile configuration section to store the first and second port configurations associated with the second port. The first port configuration can cause the second port to operate as a downstream port. The second port configuration can cause the second port to operate as an upstream port.

    ADVANCED THERMAL CONTROL FOR SSD
    5.
    发明申请

    公开(公告)号:US20220326748A1

    公开(公告)日:2022-10-13

    申请号:US17848138

    申请日:2022-06-23

    Inventor: Zhan Ping

    Abstract: A storage system with temperature control. The system includes a plurality of storage devices such as solid state drives, a system controller such as a baseboard management controller, and one or more cooling fans. Each storage devices includes a controller configured to estimate the heat load in the storage device and/or an effective temperature, resulting from operations performed in the storage device. The system controller employs active disturbance rejection control to adjust the fan speed based on the estimated heat loads, the estimated temperatures, and/or the sensed internal temperatures, of the storage devices.

    Active disturbance rejection based thermal control

    公开(公告)号:US10809780B2

    公开(公告)日:2020-10-20

    申请号:US15961782

    申请日:2018-04-24

    Abstract: A system and method for active disturbance rejection based thermal control is configured to receive, at a first active disturbance rejection thermal control (ADRC) controller, a first temperature measurement from a first thermal zone. The ADRC controller generates a first output control signal for controlling a first cooling element, wherein the first output control signal is generated according a first estimated temperature and a first estimated disturbance calculated by a first extended state observer (ESO) of the first ADRC controller.

    Memory devices and modules
    10.
    发明授权

    公开(公告)号:US10002044B2

    公开(公告)日:2018-06-19

    申请号:US14678977

    申请日:2015-04-04

    CPC classification number: G06F11/10 G06F11/1008 G06F11/1076

    Abstract: A memory module includes a module error interface, a module data interface, and a plurality of memory device. The module error interface communicates error information a system control path. The module data interface communicates data to and from a main memory path that is separate from the system control path. Each memory device includes a device controller, a device error interface and a device data interface in which the error data interface is separate from the device data interface. Each device controller includes an ECC engine and an ECC controller. The ECC engine corrects an error in data that is read from the corresponding memory device to generate corrected data, generate error information, communicate the error information through the device error interface to the module error interface, and communicate the corrected data through the device data interface to the module data interface. The ECC controller records the error information.

Patent Agency Ranking