公开(公告)号：US09449987B1

公开(公告)日：2016-09-20

申请号：US14995017

申请日：2016-01-13

申请人： SANDISK TECHNOLOGIES INC.

发明人： Koji Miyata ,  Zhenyu Lu ,  Andrew Lin ,  Daxin Mao ,  Jixin Yu ,  Johann Alsmeier ,  Wenguang Stephen Shi

IPC分类号： H01L27/115 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

摘要： A method of fabricating a memory device is provided. The method includes forming a first alternating stack of insulator layers and spacer material layers over a semiconductor substrate, etching the first alternating stack to expose a single crystalline semiconductor material, forming a first epitaxial semiconductor pedestal on the single crystalline semiconductor material, such that the first epitaxial semiconductor pedestal is in epitaxial alignment with the single crystalline semiconductor material, forming an array of memory stack structures through the first alternating stack, and forming at least one semiconductor device over the first epitaxial semiconductor pedestal.

摘要翻译： 提供一种制造存储器件的方法。 该方法包括在半导体衬底上形成绝缘体层和隔离材料层的第一交替叠层，蚀刻第一交替堆叠以暴露单晶半导体材料，在单晶半导体材料上形成第一外延半导体基座，使得第一 外延半导体基座与单晶半导体材料进行外延对准，通过第一交替叠层形成存储堆栈结构的阵列，并在第一外延半导体基座上形成至少一个半导体器件。

公开(公告)号：US09728551B1

公开(公告)日：2017-08-08

申请号：US15015190

申请日：2016-02-04

申请人： SANDISK TECHNOLOGIES INC.

发明人： Ching-Huang Lu ,  Zhenyu Lu ,  Jixin Yu ,  Daxin Mao ,  Johann Alsmeier ,  Wenguang Stephen Shi ,  Henry Chien

IPC分类号： H01L29/74 ,  H01L29/80 ,  H01L29/792 ,  H01L21/00 ,  H01L21/336 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/522 ,  H01L29/788 ,  H01L29/04 ,  H01L21/28 ,  H01L21/225 ,  H01L21/30 ,  H01L21/02 ,  H01L27/11524 ,  H01L27/1157

CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/2251 ,  H01L21/3003 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157

摘要： A memory opening can be formed through a multiple tier structure. Each tier structure includes an alternating stack of sacrificial material layers and insulating layers. After formation of a dielectric oxide layer, the memory opening is filled with a sacrificial memory opening fill structure. The sacrificial material layers are removed selective to the insulating layers and the dielectric oxide layer to form backside recesses. Physically exposed portions of the dielectric oxide layer are removed. A backside blocking dielectric and electrically conductive layers are formed in the backside recesses. Subsequently, the sacrificial memory opening fill structure is replaced with a memory stack structure including a plurality of charge storage regions and a semiconductor channel. Hydrogen or deuterium from a dielectric core may then be outdiffused into the semiconductor channel.

公开(公告)号：US09530790B1

公开(公告)日：2016-12-27

申请号：US14757572

申请日：2015-12-24

申请人： SANDISK TECHNOLOGIES INC.

发明人： Zhenyu Lu ,  Andrew Lin ,  Johann Alsmeier ,  Peter Rabkin ,  Wei Zhao ,  Wenguang Stephen Shi ,  Henry Chien ,  Jian Chen

IPC分类号： H01L29/78 ,  H01L27/115 ,  H01L23/528 ,  H01L29/08 ,  H01L29/417 ,  G11C16/24 ,  G11C16/08 ,  H01L23/522 ,  H01L29/04 ,  H01L29/786 ,  H01L29/788 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/78672 ,  H01L29/7883

摘要： Peripheral devices for a three-dimensional memory device can be formed over an array of memory stack structures to increase areal efficiency of a semiconductor chip. First contact via structures and first metal lines are formed over an array of memory stack structures and an alternating stack of insulating layers and electrically conductive layers. A semiconductor material layer including a single crystalline semiconductor material or a polycrystalline semiconductor material is formed over first metal lines. After formation of semiconductor devices on or in the semiconductor material layer, metal interconnect structures including second metal lines and additional conductive via structures are formed to electrically connect nodes of the semiconductor devices to respective first metal lines and to memory devices underneath.

摘要翻译： 用于三维存储器件的外围器件可以形成在存储器堆叠结构的阵列上，以增加半导体芯片的面积效率。 通过结构和第一金属线的第一接触形成在存储器堆叠结构的阵列和绝缘层和导电层的交替堆叠之上。 在第一金属线上形成包括单晶半导体材料或多晶半导体材料的半导体材料层。 在半导体材料层上或半导体材料层中形成半导体器件之后，形成包括第二金属线和附加导电通路结构的金属互连结构，以将半导体器件的节点电连接到相应的第一金属线和下面的存储器件。