-
1.发明授权公开(公告)号：US09941295B2
公开(公告)日：2018-04-10
申请号：US14733335
申请日：2015-06-08
IPC分类号： H01L21/336 , H01L27/11582 , H01L21/28 , H01L29/778 , H01L29/792 , H01L21/02 , H01L29/06
CPC分类号： H01L27/11582 , H01L21/0214 , H01L21/0217 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/02546 , H01L21/02584 , H01L21/0262 , H01L21/28282 , H01L27/11573 , H01L29/0649 , H01L29/0657 , H01L29/7788 , H01L29/7789 , H01L29/7926
摘要： A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.
-
2.发明授权公开(公告)号：US09876025B2
公开(公告)日：2018-01-23
申请号：US14886609
申请日：2015-10-19
IPC分类号： H01L21/00 , H01L27/11582 , H01L27/11556 , H01L29/49 , H01L29/788
CPC分类号： H01L27/11582 , H01L27/11556 , H01L27/1157 , H01L29/4916 , H01L29/7883
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate. After formation of memory film layers, a sacrificial cover material layer can be employed to protect the tunneling dielectric layer during formation of a bottom opening in the memory film layers. An amorphous semiconductor material layer can be deposited and optionally annealed in an ambient including argon and/or deuterium to form a semiconductor channel layer having a thickness less than 5 nm and surface roughness less than 10% of the thickness. Alternately or additionally, at least one interfacial layer can be employed on either side of the amorphous semiconductor material layer to reduce surface roughness of the semiconductor channel. The ultrathin channel can have enhanced mobility due to quantum confinement effects.
-
3.发明授权公开(公告)号：US09870945B2
公开(公告)日：2018-01-16
申请号：US14643280
申请日：2015-03-10
IPC分类号： H01L29/792 , H01L29/78 , H01L21/28 , H01L21/336 , H01L21/768 , H01L27/11582
CPC分类号： H01L21/76883 , H01L21/28282 , H01L21/7682 , H01L27/11582
摘要： A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity. Each electrically conductive layer contains a material from a portion of a respective second epitaxial semiconductor layer.
-
公开(公告)号：US09799671B2
公开(公告)日：2017-10-24
申请号：US14680414
申请日：2015-04-07
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L21/28 , H01L21/768 , H01L23/522 , H01L23/528 , H01L29/788
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L21/768 , H01L23/5226 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/7883
摘要： Dielectric degradation and electrical shorts due to fluorine radical generation from metallic electrically conductive lines in a three-dimensional memory device can be reduced by forming composite electrically conductive layers and/or using of a metal oxide material for an insulating spacer for backside contact trenches. Each composite electrically conductive layer includes a doped semiconductor material portion in proximity to memory stack structures and a metallic material portion in proximity to a backside contact trench. Fluorine generated from the metallic material layers can escape readily through the backside contact trench. The semiconductor material portions can reduce mechanical stress. Alternatively or additionally, a dielectric metal oxide can be employed as an insulating spacer on the sidewalls of the backside contact trench, thereby blocking a diffusion path for fluorine radicals generated from the metallic material of the electrically conductive layers, and preventing electrical shorts between electrically conductive layers and/or a backside contact via structure.
-
5.发明授权公开(公告)号：US09780182B2
公开(公告)日：2017-10-03
申请号：US14751689
申请日：2015-06-26
发明人： Somesh Peri , Raghuveer S. Makala , Sateesh Koka , Yao-Sheng Lee , Johann Alsmeier , George Matamis
IPC分类号： H01L29/49 , H01L21/28 , H01L29/792 , H01L27/11582 , H01L27/11573 , H01L27/11575 , H01L29/66 , H01L29/788 , H01L27/11556 , H01L27/11534 , H01L27/11548
CPC分类号： H01L29/4966 , H01L21/28273 , H01L21/28282 , H01L27/11534 , H01L27/11548 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A molybdenum-containing portion can be formed in each backside recess. Each backside recess can be filled with a molybdenum-containing portion alone, or can be filled with a combination of a molybdenum-containing portion and a metallic material portion including a material other than molybdenum.
-
公开(公告)号：US09780108B2
公开(公告)日：2017-10-03
申请号：US14886507
申请日：2015-10-19
IPC分类号： H01L29/792 , H01L27/1157 , H01L27/11582 , H01L29/10 , H01L29/32
CPC分类号： H01L27/1157 , H01L27/11582 , H01L29/1033 , H01L29/32
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate. After formation of memory film layers, a sacrificial cover material layer can be employed to protect the tunneling dielectric layer during formation of a bottom opening in the memory film layers. An amorphous semiconductor material layer can be deposited and optionally annealed in an ambient including argon and/or deuterium to form a semiconductor channel layer having a thickness less than 5 nm and surface roughness less than 10% of the thickness. Alternately or additionally, at least one interfacial layer can be employed on either side of the amorphous semiconductor material layer to reduce surface roughness of the semiconductor channel. The ultrathin channel can have enhanced mobility due to quantum confinement effects.
-
公开(公告)号：US09761604B2
公开(公告)日：2017-09-12
申请号：US14666678
申请日：2015-03-24
IPC分类号： H01L29/423 , H01L27/11582 , H01L27/06 , H01L29/201 , H01L27/1157 , H01L29/792 , H01L29/51
CPC分类号： H01L27/11582 , H01L27/0605 , H01L27/1157 , H01L29/201 , H01L29/517 , H01L29/7926
摘要： Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.
-
公开(公告)号：US09728551B1
公开(公告)日：2017-08-08
申请号：US15015190
申请日：2016-02-04
发明人： Ching-Huang Lu , Zhenyu Lu , Jixin Yu , Daxin Mao , Johann Alsmeier , Wenguang Stephen Shi , Henry Chien
IPC分类号： H01L29/74 , H01L29/80 , H01L29/792 , H01L21/00 , H01L21/336 , H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L27/11565 , H01L23/528 , H01L23/522 , H01L29/788 , H01L29/04 , H01L21/28 , H01L21/225 , H01L21/30 , H01L21/02 , H01L27/11524 , H01L27/1157
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02236 , H01L21/2251 , H01L21/3003 , H01L23/5226 , H01L23/528 , H01L27/1157
摘要： A memory opening can be formed through a multiple tier structure. Each tier structure includes an alternating stack of sacrificial material layers and insulating layers. After formation of a dielectric oxide layer, the memory opening is filled with a sacrificial memory opening fill structure. The sacrificial material layers are removed selective to the insulating layers and the dielectric oxide layer to form backside recesses. Physically exposed portions of the dielectric oxide layer are removed. A backside blocking dielectric and electrically conductive layers are formed in the backside recesses. Subsequently, the sacrificial memory opening fill structure is replaced with a memory stack structure including a plurality of charge storage regions and a semiconductor channel. Hydrogen or deuterium from a dielectric core may then be outdiffused into the semiconductor channel.
-
公开(公告)号：US09728546B2
公开(公告)日：2017-08-08
申请号：US14748670
申请日：2015-06-24
发明人： Andrey Serov , James K. Kai , Yanli Zhang , Henry Chien , Johann Alsmeier
IPC分类号： H01L27/115 , H01L27/11556 , H01L27/11582 , H01L27/11565 , H01L27/11519 , G11C16/04 , H01L29/66 , H01L27/11524 , H01L27/1157 , G11C16/14
CPC分类号： H01L27/11556 , G11C16/0408 , G11C16/0483 , G11C16/14 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/66666 , H01L29/66825 , H01L29/7827
摘要： A three dimensional NAND device includes a common vertical channel and electrically isolated control gate electrodes on different lateral sides of the channel in each device level to form different lateral portions of a memory cell in each device level. Dielectric separator structures are located between and electrically isolate the control gate electrodes. The lateral portions of the memory cell in each device level may be electrically isolated by at least one of doping ungated portions of the channel adjacent to the separator structures or storing electrons in the separator structure.
-
10.发明授权公开(公告)号：US09698153B2
公开(公告)日：2017-07-04
申请号：US15080269
申请日：2016-03-24
IPC分类号： H01L27/00 , H01L27/1157 , H01L27/11582 , H01L21/28 , H01L21/822 , H01L27/11551 , H01L27/06 , H01L27/11524 , H01L27/11578 , H01L29/66 , H01L29/788 , H01L29/792 , H01L27/11556
CPC分类号： H01L27/1157 , H01L21/28273 , H01L21/8221 , H01L27/0688 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L2224/32145
摘要： Alignment between memory openings through multiple tier structures can be facilitated employing a temporary landing pad. The temporary landing pad can have a greater area than the horizontal cross-sectional area of a first memory opening through a first tier structure including a first alternating stack of first insulating layers and first spacer material layers. An upper portion of a first memory film is removed, and a sidewall of an insulating cap layer that defines the first memory opening can be laterally recessed to form a recessed cavity. A sacrificial fill material is deposited in the recessed cavity to form a sacrificial fill material portion, which functions as the temporary landing pad for a second memory opening that is subsequently formed through a second tier structure including second insulating layers and second spacer material layers. A memory stack structure can be formed through the first and second tier structures.
-
-
-
-
-
-
-
-
-
搜索结果
157 条记录 (耗时 0.04 秒)