公开(公告)号：US20200295040A1

公开(公告)日：2020-09-17

申请号：US16886824

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akihiro Tobioka

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L21/311 ,  H01L23/532 ,  H01L23/528 ,  H01L21/033 ,  H01L27/11565 ,  H01L23/48

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. A pair of backside trenches and a set of nested trenches are simultaneously formed through the alternating stack. Each trench within the set of nested trenches is spaced from any other trench within the set of nested trenches by at least one patterned remaining portion of the alternating stack having a respective shape of an enclosing wall. The at least one patterned remaining portion of the alternating stack is removed from inside to outside using sequential etch processes. A dielectric pillar structure is formed within the pillar-shaped cavity. The sacrificial material layers are replaced with electrically conductive layers. A through-memory-level conductive via structure is formed through the dielectric pillar structure.

公开(公告)号：US10274841B2

公开(公告)日：2019-04-30

申请号：US15724488

申请日：2017-10-04

Applicant: SanDisk Technologies LLC

Inventor： Akihiro Tobioka

IPC: G03F7/20 ,  G02B5/02 ,  G03F1/44 ,  G02B27/32

Abstract: A reticle for a semiconductor lithography process includes a glass plate having regions with a reduced optical transmission factor. The regions may include arrays of elements comprising defects such as cracks or voids which are formed by laser pulses. The regions may be adjacent to openings in an opaque material at the bottom of the reticle to shield the openings from a portion of the light which illuminates the reticle from the top. As a result, the light which exits the reticle and is used to pattern a substrate has an asymmetric intensity. This allows the substrate to be patterned with an inspection mark which indicates whether a defocus condition exists, and whether there is a positive or negative defocus condition. Related methods use a reticle to form a pattern on a substrate and for adjusting a focus condition using a reticle.

公开(公告)号：US11749600B2

公开(公告)日：2023-09-05

申请号：US17224370

申请日：2021-04-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akihiro Tobioka

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: A vertically alternating sequence of unit layer stacks is formed over a substrate. Each unit layer stacks includes an insulating layer and a spacer material layer that is formed as, or is subsequently replaced with, a first electrically conductive layer. A 2×N array of stepped surfaces is formed. Each column of two stepped surfaces other than one column is vertically extended by performing a set of processing sequences at least once. The set of processing sequences includes forming a patterned etch mask layer and etching an unmasked subset of the 2×N array. One or more patterned etch mask layer has a respective continuous opening including an entire area of a respective 2×M array of stepped surfaces that is a subset of the 2×N array of stepped surfaces. Vertical stacks of memory elements are formed through the vertically alternating sequence.

公开(公告)号：US10861871B2

公开(公告)日：2020-12-08

申请号：US16353048

申请日：2019-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akihiro Tobioka

IPC: H01L21/461 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/033 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. A pair of backside trenches and a set of nested trenches are simultaneously formed through the alternating stack. Each trench within the set of nested trenches is spaced from any other trench within the set of nested trenches by at least one patterned remaining portion of the alternating stack having a respective shape of an enclosing wall. The at least one patterned remaining portion of the alternating stack is removed from inside to outside using sequential etch processes. A dielectric pillar structure is formed within the pillar-shaped cavity. The sacrificial material layers are replaced with electrically conductive layers. A through-memory-level conductive via structure is formed through the dielectric pillar structure.

公开(公告)号：US11495612B2

公开(公告)日：2022-11-08

申请号：US16918463

申请日：2020-07-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshinobu Tanaka ,  Koichi Ito ,  Hideaki Hasegawa ,  Akihiro Tobioka ,  Sung Tae Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11529

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

公开(公告)号：US11450679B2

公开(公告)日：2022-09-20

申请号：US16918493

申请日：2020-07-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshinobu Tanaka ,  Koichi Ito ,  Hideaki Hasegawa ,  Akihiro Tobioka ,  Sung Tae Lee

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11529 ,  H01L21/311 ,  H01L27/11573

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.

公开(公告)号：US11189637B2

公开(公告)日：2021-11-30

申请号：US16886824

申请日：2020-05-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akihiro Tobioka

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/033 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. A pair of backside trenches and a set of nested trenches are simultaneously formed through the alternating stack. Each trench within the set of nested trenches is spaced from any other trench within the set of nested trenches by at least one patterned remaining portion of the alternating stack having a respective shape of an enclosing wall. The at least one patterned remaining portion of the alternating stack is removed from inside to outside using sequential etch processes. A dielectric pillar structure is formed within the pillar-shaped cavity. The sacrificial material layers are replaced with electrically conductive layers. A through-memory-level conductive via structure is formed through the dielectric pillar structure.

公开(公告)号：US20200295032A1

公开(公告)日：2020-09-17

申请号：US16353048

申请日：2019-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akihiro Tobioka

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/033 ,  H01L23/532 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. A pair of backside trenches and a set of nested trenches are simultaneously formed through the alternating stack. Each trench within the set of nested trenches is spaced from any other trench within the set of nested trenches by at least one patterned remaining portion of the alternating stack having a respective shape of an enclosing wall. The at least one patterned remaining portion of the alternating stack is removed from inside to outside using sequential etch processes. A dielectric pillar structure is formed within the pillar-shaped cavity. The sacrificial material layers are replaced with electrically conductive layers. A through-memory-level conductive via structure is formed through the dielectric pillar structure.

公开(公告)号：US12255154B2

公开(公告)日：2025-03-18

申请号：US17510833

申请日：2021-10-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akihiro Tobioka ,  Yusuke Tanaka

IPC: H10B41/27 ,  H01L23/00 ,  H10B43/27

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings and support openings are formed through the alternating stack. The memory openings are arranged in a first hexagonal array having a nearest-neighbor direction that is parallel to a first horizontal direction, and the support openings are arranged in a second hexagonal array having a nearest-neighbor direction that is perpendicular to the first horizontal direction. Memory opening fill structures are formed within a respective one of the memory openings, and support pillar structures within a respective one of the support openings.

公开(公告)号：US12010842B2

公开(公告)日：2024-06-11

申请号：US17166357

申请日：2021-02-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akihiro Tobioka ,  Akira Yoshida

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A method includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming a joint dielectric layer over the first-tier alternating stack, such that the joint dielectric layer is thicker than each of the first insulating layers and the first sacrificial material layers, forming a second-tier alternating stack of second insulating layers and second sacrificial material layers over the joint dielectric layer and the first-tier alternating stack, performing a level-shift anisotropic etch process to form a recess trench or via cavities vertically extending through the second-tier alternating stack and down to the joint dielectric layer, and performing an extension etching process to extend the recess trench or the via cavities through at least the joint dielectric level. At least one of etching time or etching power used during the extension etching process is different from that used during the level-shift anisotropic etch process.