公开(公告)号：US10673434B2

公开(公告)日：2020-06-02

申请号：US16145839

申请日：2018-09-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiv Harit Mathur ,  Anand Sharma

IPC: H03K19/00 ,  H03K19/003 ,  G11C7/10

Abstract: A circuit or associated system or method comprises a first driver including a first transistor bank and a first resistor connected in series between a first predetermined voltage and an output pad, the first transistor bank including a first driver transistor and a plurality of first calibration transistors, wherein the plurality of first calibration transistors are respectively controlled based on a combination of bits of a first calibration code and on an output of at least one first logic gate.

公开(公告)号：US20200106438A1

公开(公告)日：2020-04-02

申请号：US16145839

申请日：2018-09-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiv Harit Mathur ,  Anand Sharma

IPC: H03K19/00 ,  G11C7/10 ,  H03K19/003

Abstract: A circuit or associated system or method comprises a first driver including a first transistor bank and a first resistor connected in series between a first predetermined voltage and an output pad, the first transistor bank including a first driver transistor and a plurality of first calibration transistors, wherein the plurality of first calibration transistors are respectively controlled based on a combination of bits of a first calibration code and on an output of at least one first logic gate.

公开(公告)号：US20170255741A1

公开(公告)日：2017-09-07

申请号：US15172974

申请日：2016-06-03

Applicant: SanDisk Technologies LLC

Inventor： Anand Sharma ,  Shiv Harit Mathur ,  Rajeswara Rao Bandaru

IPC: G06F17/50 ,  H02H9/04

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/70 ,  H01L27/0248 ,  H01L27/0251

Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.

公开(公告)号：US10129012B2

公开(公告)日：2018-11-13

申请号：US15473067

申请日：2017-03-29

Applicant: SanDisk Technologies LLC

Inventor： Krishnamurthy Dhakshinamurthy ,  Shajith Musaliar Sirajudeen ,  Jayaprakash Naradasi ,  Bhavin Odedara ,  Yosi Pinto ,  Rampraveen Somasundaram ,  Anand Sharma

IPC: H04L7/00

Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.

公开(公告)号：US20180302093A1

公开(公告)日：2018-10-18

申请号：US15626580

申请日：2017-06-19

Applicant: SanDisk Technologies LLC

Inventor： Shiv Harit Mathur ,  Anand Sharma ,  Ramakrishnan Karungulam Subramanian ,  Nitin Gupta

IPC: H03K19/0185 ,  H03K19/21

Abstract: A circuit may receive control signals to generate an output signal with pulses corresponding to pulses of a source signal. The circuit may include a primary circuit and an auxiliary circuit. The primary circuit may constantly participate in the generation of pulses of the output signal. The auxiliary circuit may selectively participate with the primary circuit in the generation of the pulses. For two consecutive pulses of the output signal, whether the auxiliary circuit participates in generating the latter of the two pulses may depend on whether a threshold level is crossed during generation of the consecutive pulses.

公开(公告)号：US09996655B2

公开(公告)日：2018-06-12

申请号：US15172974

申请日：2016-06-03

Applicant: SanDisk Technologies LLC

Inventor： Anand Sharma ,  Shiv Harit Mathur ,  Rajeswara Rao Bandaru

IPC: G06F9/455 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/70 ,  H01L27/0248 ,  H01L27/0251

Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.

公开(公告)号：US20180083764A1

公开(公告)日：2018-03-22

申请号：US15473067

申请日：2017-03-29

Applicant: SanDisk Technologies LLC

Inventor： Krishnamurthy Dhakshinamurthy ,  Shajith Musaliar Sirajudeen ,  Jayaprakash Naradasi ,  Bhavin Odedara ,  Yosi Pinto ,  Rampraveen Somasundaram ,  Anand Sharma

IPC: H04L7/00

CPC classification number: H04L7/0012 ,  G06F1/12 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0337

Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.