公开(公告)号：US11916549B1

公开(公告)日：2024-02-27

申请号：US17898263

申请日：2022-08-29

Applicant: SanDisk Technologies LLC

Inventor： Shiv Harit Mathur ,  Sai Ravi Teja Konakalla

IPC: H03K19/0185 ,  H03K3/037

CPC classification number: H03K19/018521 ,  H03K3/037

Abstract: Improved voltage level shifters are disclosed capable of achieving substantially higher data transfer speeds with reduced static current than existing cross-coupled voltage level shifters. The voltage level shifters disclosed herein include first stage that translates input voltage signals received from a core circuitry in a first voltage domain to intermediate output voltage signals an intermediate voltage domain, and second stage circuitry that translates the intermediate output voltage signals received from the first stage circuitry in the intermediate voltage domain to output voltage signals in a second voltage domain. The disclosed voltage level shifters are scalable to support various logic voltage levels in the second voltage domain.

公开(公告)号：US20170255741A1

公开(公告)日：2017-09-07

申请号：US15172974

申请日：2016-06-03

Applicant: SanDisk Technologies LLC

Inventor： Anand Sharma ,  Shiv Harit Mathur ,  Rajeswara Rao Bandaru

IPC: G06F17/50 ,  H02H9/04

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/70 ,  H01L27/0248 ,  H01L27/0251

Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.

公开(公告)号：US10673434B2

公开(公告)日：2020-06-02

申请号：US16145839

申请日：2018-09-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiv Harit Mathur ,  Anand Sharma

IPC: H03K19/00 ,  H03K19/003 ,  G11C7/10

Abstract: A circuit or associated system or method comprises a first driver including a first transistor bank and a first resistor connected in series between a first predetermined voltage and an output pad, the first transistor bank including a first driver transistor and a plurality of first calibration transistors, wherein the plurality of first calibration transistors are respectively controlled based on a combination of bits of a first calibration code and on an output of at least one first logic gate.

公开(公告)号：US20200106438A1

公开(公告)日：2020-04-02

申请号：US16145839

申请日：2018-09-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiv Harit Mathur ,  Anand Sharma

IPC: H03K19/00 ,  G11C7/10 ,  H03K19/003

Abstract: A circuit or associated system or method comprises a first driver including a first transistor bank and a first resistor connected in series between a first predetermined voltage and an output pad, the first transistor bank including a first driver transistor and a plurality of first calibration transistors, wherein the plurality of first calibration transistors are respectively controlled based on a combination of bits of a first calibration code and on an output of at least one first logic gate.

公开(公告)号：US10348276B2

公开(公告)日：2019-07-09

申请号：US15858070

申请日：2017-12-29

Applicant: SanDisk Technologies LLC

Inventor： Shiv Harit Mathur

IPC: H03K5/00 ,  H03K5/13 ,  G06F13/38 ,  H03K3/353

Abstract: A clock-receiving system may receive a host clock signal on a communications bus from a clock-sending system. Circuitry of a critical path of the clock-receiving system may communicate the clock signal to a multiplexer configured directly behind output driver circuitry. Core logic circuitry and data path circuitry may communicate pairs of phase-shifted data signals to the multiplexer. The multiplexer may use the clock signal and the pairs of phase-shifted data signals to generate an output pair of data signals, and send the output pair of data signals to the output driver circuitry. In turn, the output driver circuitry may generate an output data signal for communication on the communications bus. The clock-receiving system may enable the critical path and use the multiplexer to generate the output data signal when in a low operating voltage mode.

公开(公告)号：US20180302093A1

公开(公告)日：2018-10-18

申请号：US15626580

申请日：2017-06-19

Applicant: SanDisk Technologies LLC

Inventor： Shiv Harit Mathur ,  Anand Sharma ,  Ramakrishnan Karungulam Subramanian ,  Nitin Gupta

IPC: H03K19/0185 ,  H03K19/21

Abstract: A circuit may receive control signals to generate an output signal with pulses corresponding to pulses of a source signal. The circuit may include a primary circuit and an auxiliary circuit. The primary circuit may constantly participate in the generation of pulses of the output signal. The auxiliary circuit may selectively participate with the primary circuit in the generation of the pulses. For two consecutive pulses of the output signal, whether the auxiliary circuit participates in generating the latter of the two pulses may depend on whether a threshold level is crossed during generation of the consecutive pulses.

公开(公告)号：US09996655B2

公开(公告)日：2018-06-12

申请号：US15172974

申请日：2016-06-03

Applicant: SanDisk Technologies LLC

Inventor： Anand Sharma ,  Shiv Harit Mathur ,  Rajeswara Rao Bandaru

IPC: G06F9/455 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/70 ,  H01L27/0248 ,  H01L27/0251

Abstract: A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the circuit components of the I/O cells. In this way, the design of ESD protection circuitry may be optimized without having to redo a completed I/O cell design and significantly delay the design flow before tapeout.

公开(公告)号：US12191854B2

公开(公告)日：2025-01-07

申请号：US17949990

申请日：2022-09-21

Applicant: SanDisk Technologies LLC

Inventor： Nirav Natwarbhai Patel ,  Shiv Harit Mathur ,  Sai Ravi Teja Konakalla

IPC: H03K19/00 ,  G11C7/10 ,  G11C16/04

Abstract: Systems and methods for improving the power, performance, and area (PPA) for a voltage mode driver and on die termination (ODT). A voltage mode driver having first and second circuits in a pulldown design. The first circuit has a plurality of nMOS devices in parallel, the plurality of nMOS devices being common to a first resistor. The second circuit is in parallel with the first circuit and has an nMOS device in series with a second resistor. The second circuit is configured to be enabled when the pulldown impedance of the first circuit, with the second circuit disabled and all of the nMOS devices of the first circuit turned on, is greater than a desired pulldown impedance. The voltage mode driver may also be a pullup design, or have both pulldown and pullup stages.

公开(公告)号：US11984168B2

公开(公告)日：2024-05-14

申请号：US17835324

申请日：2022-06-08

Applicant: SanDisk Technologies LLC

Inventor： Nitin Gupta ,  Shiv Harit Mathur ,  Ramakrishnan Subramanian ,  Dmitry Vaysman

IPC: G11C7/10 ,  G11C11/16 ,  G11C16/30

CPC classification number: G11C16/30 ,  G11C7/1096 ,  G11C11/1697

Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.

公开(公告)号：US20230198524A1

公开(公告)日：2023-06-22

申请号：US17553630

申请日：2021-12-16

Applicant: SanDisk Technologies LLC

Inventor： Shiv Harit Mathur

IPC: H03K19/0175 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K19/017509 ,  H03K3/037 ,  H03K19/20

Abstract: An improved cross-coupled voltage level shifter is disclosed that is capable of achieving substantially higher data transfer speeds with reduced transistor sizes than existing cross-coupled voltage level shifters. The voltage level shifter includes a cross-coupled latch, control circuitry that initiates a state transition of the latch responsive to activation, where the control circuitry is activated by a change in a logic voltage level of an input signal to the voltage level shifter, and feedback circuitry that reinforces the latch action of the cross-coupled latch. The control circuitry may include pull-down transistors that are thin-gate devices, and thus, substantially smaller in area than what would otherwise be needed to meet the large current requirement of the pull-down transistors as compared to latch transistors of the latch.