公开(公告)号：US20220415718A1

公开(公告)日：2022-12-29

申请号：US17725695

申请日：2022-04-21

Applicant: SanDisk Technologies LLC

Inventor： Cheng-Chung Chu ,  Masaaki Higashitani ,  Yusuke Ikawa ,  Seyyed Ehsan Esfahani Rashidi ,  Kei Samura ,  Tsuyoshi Sendoda ,  Yanli Zhang

IPC: H01L21/66 ,  H01L27/11578

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

公开(公告)号：US11947890B2

公开(公告)日：2024-04-02

申请号：US16870070

申请日：2020-05-08

Applicant: SanDisk Technologies LLC

Inventor： Cheng-Chung Chu ,  Janet George ,  Daniel J. Linnen ,  Ashish Ghai

IPC: G06F30/398 ,  G06F119/22 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  H01L21/66

CPC classification number: G06F30/398 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  H01L22/12 ,  G06F2119/22

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

公开(公告)号：US20240202425A1

公开(公告)日：2024-06-20

申请号：US18586736

申请日：2024-02-26

Applicant: SanDisk Technologies LLC

Inventor： Cheng-Chung Chu ,  Janet George ,  Daniel J. Linnen ,  Ashish Ghai

IPC: G06F30/398 ,  G06F119/22 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  H01L21/66

CPC classification number: G06F30/398 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  H01L22/12 ,  G06F2119/22

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

公开(公告)号：US20210397170A1

公开(公告)日：2021-12-23

申请号：US17465305

申请日：2021-09-02

Applicant: SanDisk Technologies LLC

Inventor： Fei Zhou ,  Cheng-Chung Chu ,  Raghuveer Makala

IPC: G05B19/418 ,  G05B13/02 ,  H01L21/66

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

公开(公告)号：US12124247B2

公开(公告)日：2024-10-22

申请号：US17465305

申请日：2021-09-02

Applicant: SanDisk Technologies LLC

Inventor： Fei Zhou ,  Cheng-Chung Chu ,  Raghuveer Makala

IPC: G05B19/418 ,  G05B13/02 ,  H01L21/66

CPC classification number: G05B19/41875 ,  G05B13/027 ,  H01L22/20 ,  G05B2219/32335 ,  G05B2219/32368 ,  G05B2219/45031

Abstract: Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

公开(公告)号：US12009269B2

公开(公告)日：2024-06-11

申请号：US17725695

申请日：2022-04-21

Applicant: SanDisk Technologies LLC

Inventor： Cheng-Chung Chu ,  Masaaki Higashitani ,  Yusuke Ikawa ,  Seyyed Ehsan Esfahani Rashidi ,  Kei Samura ,  Tsuyoshi Sendoda ,  Yanli Zhang

IPC: H01L21/66 ,  H01L27/11578 ,  H10B43/20 ,  H10B43/10

CPC classification number: H01L22/14 ,  H01L22/12 ,  H01L22/26 ,  H10B43/20 ,  H10B43/10

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

公开(公告)号：US10103161B2

公开(公告)日：2018-10-16

申请号：US15195377

申请日：2016-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitoshi Ito ,  Masaaki Higashitani ,  Cheng-Chung Chu ,  Jayavel Pachamuthu ,  Tuan Pham

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/535 ,  H01L29/06

Abstract: Die cracking of a three dimensional memory device may be reduced by adding offsets to backside contact via structures. Each backside contact via structure can include laterally extending portions that extend along a first horizontal direction adjoined by adjoining portions that extend along a horizontal direction other than the first horizontal direction. In order to preserve periodicity of memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers, the distance between an outermost row of a string of memory stack structures between a pair of backside contact via structures and a most proximal backside contact via structure can vary from a laterally extending portion to another laterally extending portion within the most proximal backside contact via structure. Source shunt lines that are parallel to bit lines can be formed over a selected subset of offset portions of the backside contact via structures.

公开(公告)号：US10014316B2

公开(公告)日：2018-07-03

申请号：US15296380

申请日：2016-10-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fabo Yu ,  Jayavel Pachamuthu ,  Jongsun Sel ,  Tuan Pham ,  Cheng-Chung Chu ,  Yao-Sheng Lee ,  Kensuke Yamaguchi ,  Masanori Terahara ,  Shuji Minagawa

IPC: H01L27/115 ,  H01L21/768 ,  H01L23/532 ,  H01L21/336 ,  H01L29/167 ,  H01L21/28 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11582 ,  H01L27/11556 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/11575 ,  H01L21/76229 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/78

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

公开(公告)号：US09917093B2

公开(公告)日：2018-03-13

申请号：US15195446

申请日：2016-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Cheng-Chung Chu ,  Jayavel Pachamuthu ,  Tuan Pham ,  Fumitoshi Ito ,  Masaaki Higashitani

IPC: H01L29/788 ,  H01L27/11556 ,  H01L23/522 ,  H01L21/22 ,  H01L21/768 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/417

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three-dimensional memory device includes a plurality of planes, each having a respective alternating stack, strings of memory stack structures which extends through the respective alternating stack, and backside contact via structures vertically extending through the respective alternating stack, extending generally along the first horizontal direction, and laterally separating neighboring pairs of strings of memory stack structures along a second horizontal direction. A first plane includes a first plurality of strings that are laterally spaced apart along the second horizontal direction by a first plurality of backside contact via structures. A second plane laterally shifted from the first plane along the first horizontal direction and including a second plurality of strings that are laterally spaced apart along the second horizontal direction by a second plurality of backside contact via structures which are laterally offset with respect the first plurality of backside contact via structures along the second horizontal direction.