公开(公告)号：US20210358937A1

公开(公告)日：2021-11-18

申请号：US17134938

申请日：2020-12-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kohei YAMAGUCHI ,  Keisuke SHIGEMURA ,  Kengo KAJIWARA

IPC: H01L27/11575 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L23/00

Abstract: A row of backside support pillar structures is formed through a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers. At least one upper-tier alternating stack can be formed, and memory stack structures can be formed through the alternating stacks. A backside trench can be formed through the alternating stacks selective to the row of backside support pillar structures. The sacrificial material layers are replaced with electrically conductive layers, and the backside trench can be filled with a backside trench fill structure, which includes the row of backside support pillar structures. The row of backside support pillar structures reduces or prevents tilting or collapse of the alternating stacks during replacement of the sacrificial material layers with the electrically conductive layers.

公开(公告)号：US20200312765A1

公开(公告)日：2020-10-01

申请号：US16516726

申请日：2019-07-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Motoki KAWASAKI ,  Arata OKUYAMA ,  Xun GU ,  Kengo KAJIWARA ,  Jixin YU

IPC: H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers located over a semiconductor region, and laterally spaced from each other by a backside trench, memory stack structures extending through the pair of alternating, each memory stack structure containing a vertical semiconductor channel and a memory film, and a backside contact assembly located in the backside trench. The backside contact assembly includes an isolation dielectric spacer contacting the pair of alternating stacks, a conductive liner contacting inner sidewalls of the isolation dielectric spacer and a top surface of the semiconductor region, and composite non-metallic core containing at least one outer dielectric fill material portion that is laterally enclosed by a lower portion of the conductive liner and a dielectric core contacting an inner sidewall of the at least one outer dielectric fill material portion.

公开(公告)号：US20240332180A1

公开(公告)日：2024-10-03

申请号：US18624522

申请日：2024-04-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Teruo OKINA ,  Kengo KAJIWARA

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a source layer; a memory opening vertically extending through the alternating stack; and a memory opening fill structure located in the memory opening and including a memory film, a vertical semiconductor channel laterally surrounded by the memory film and in contact with the source layer, a dielectric metal oxide liner laterally surrounded by the vertical semiconductor channel, and a dielectric core laterally surrounded by the dielectric metal oxide liner.

公开(公告)号：US20240099014A1

公开(公告)日：2024-03-21

申请号：US18524552

申请日：2023-11-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shunsuke TAKUMA ,  Yuji TOTOKI ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE ,  Kengo KAJIWARA ,  Akihiro TOBIOKA

IPC: H10B43/50 ,  H01L23/00 ,  H01L23/522 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

CPC classification number: H10B43/50 ,  H01L23/5226 ,  H01L23/562 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.

公开(公告)号：US20220223614A1

公开(公告)日：2022-07-14

申请号：US17146866

申请日：2021-01-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shunsuke TAKUMA ,  Yuji TOTOKI ,  Seiji SHIMABUKURO ,  Tatsuya HINOUE ,  Kengo KAJIWARA ,  Akihiro TOBIOKA

IPC: H01L27/11575 ,  H01L23/522 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582

Abstract: At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.

公开(公告)号：US20210358941A1

公开(公告)日：2021-11-18

申请号：US16876370

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kengo KAJIWARA ,  Atsushi SHIMODA ,  Tatsuya HINOUE ,  Junpei KANAZAWA ,  Masanori TERAHARA

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768

Abstract: A three-dimensional memory device includes a first-tier structure located over a substrate and including a first alternating stack of first insulating layers and first electrically conductive layers. a second-tier structure located over the first-tier structure and including a second alternating stack of second insulating layers and second electrically conductive layers, memory stack structures vertically extending through the first alternating stack and the second alternating stack, primary support pillar structures, and auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack.

公开(公告)号：US20210358936A1

公开(公告)日：2021-11-18

申请号：US17036070

申请日：2020-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shunsuke TAKUMA ,  Seiji SHIMABUKURO ,  Kengo KAJIWARA

IPC: H01L27/11575 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582

Abstract: A alternating stack of insulating layers and sacrificial material layers is formed over a substrate. An array of memory opening fill structures and an array of support pillar structures are formed through the alternating stack. Backside trenches are formed through the alternating stack by performing an anisotropic etch process. The anisotropic etch process etches peripheral portions of a subset of the array of support pillar structures. The sacrificial material layers are replaced with electrically conductive layer by forming backside recesses while the support pillar structures provide mechanical support to the insulating layers.

公开(公告)号：US20210005627A1

公开(公告)日：2021-01-07

申请号：US16503884

申请日：2019-07-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tatsuya HINOUE ,  Kengo KAJIWARA ,  Ryosuke ITOU ,  Naohiro HOSODA ,  Yohei MASAMORI ,  Kota FUNAYAMA ,  Keisuke TSUKAMOTO ,  Hirofumi WATATANI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.