公开(公告)号：US20210210424A1

公开(公告)日：2021-07-08

申请号：US16809861

申请日：2020-03-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka OTSU ,  Masanori TERAHARA ,  Junpei KANAZAWA

IPC: H01L23/522 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers. An interconnection via structure can be laterally surrounded by the perforated dielectric moat structure, and can vertically extend through each insulating layer within the alternating stack.

公开(公告)号：US20210358941A1

公开(公告)日：2021-11-18

申请号：US16876370

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kengo KAJIWARA ,  Atsushi SHIMODA ,  Tatsuya HINOUE ,  Junpei KANAZAWA ,  Masanori TERAHARA

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768

Abstract: A three-dimensional memory device includes a first-tier structure located over a substrate and including a first alternating stack of first insulating layers and first electrically conductive layers. a second-tier structure located over the first-tier structure and including a second alternating stack of second insulating layers and second electrically conductive layers, memory stack structures vertically extending through the first alternating stack and the second alternating stack, primary support pillar structures, and auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack.

公开(公告)号：US20180108671A1

公开(公告)日：2018-04-19

申请号：US15296380

申请日：2016-10-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fabo YU ,  Jayavel PACHAMUTHU ,  Jongsun SEL ,  Tuan PHAM ,  Cheng-Chung CHU ,  Yao-Sheng LEE ,  Kensuke YAMAGUCHI ,  Masanori TERAHARA ,  Shuji MINAGAWA

IPC: H01L27/115 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/11575 ,  H01L21/76229 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/0607 ,  H01L29/0649

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.