公开(公告)号：US20230128326A1

公开(公告)日：2023-04-27

申请号：US17509323

申请日：2021-10-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka AMANO ,  Kensuke ISHIKAWA

IPC: H01L21/768 ,  H01L23/532

Abstract: A method includes forming a semiconductor device, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure consisting essentially of an elemental metal that is not copper from a physically exposed conductive surface located at a bottom of the via portion of the integrated line-and-via cavity without filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that includes copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity.

公开(公告)号：US20220399232A1

公开(公告)日：2022-12-15

申请号：US17345315

申请日：2021-06-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka AMANO ,  Yusuke OSAWA ,  Kensuke ISHIKAWA ,  Mitsuteru MUSHIGA ,  Motoki KAWASAKI ,  Shinsuke YADA ,  Masato MIYAMOTO ,  Syo FUKATA ,  Takashi KASHIMURA ,  Shigehiro FUJINO

IPC: H01L21/768 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.

公开(公告)号：US20230361069A1

公开(公告)日：2023-11-09

申请号：US17930858

申请日：2022-09-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kensuke ISHIKAWA ,  Fumitaka AMANO ,  Shingo TOTANI ,  Linghan CHEN

IPC: H01L23/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2224/05647 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/05649 ,  H01L2224/131 ,  H01L24/13

Abstract: A bonded assembly includes a first semiconductor die containing first semiconductor devices and a first bonding pad embedded within a first silicon oxide layer, where the first bonding pad includes a first copper containing portion, a second semiconductor die containing second semiconductor devices and a second bonding pad that is embedded within a second silicon oxide layer and is bonded to the first bonding pad via metal-to-metal bonding, where the second bonding pad includes a second copper containing portion, and at least one metal silicon oxide layer interposed between the first bonding pad and the second silicon oxide layer. In one embodiment, the at least one metal silicon oxide layer is a manganese silicon oxide layer.

公开(公告)号：US20230361061A1

公开(公告)日：2023-11-09

申请号：US17662501

申请日：2022-05-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shingo TOTANI ,  Fumitaka AMANO ,  Kensuke ISHIKAWA

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2924/37001 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08147 ,  H01L2224/05647 ,  H01L2224/05573 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2224/05082 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05017 ,  H01L2224/05557

Abstract: Bonding strength and yield can be enhanced by providing a mating pair of a convex bonding surface and a concave bonding surface. The convex bonding surface can be provided by employing a conductive barrier layer having a higher electrochemical potential than copper. The concave bonding surface can be provided by employing a conductive barrier layer having a lower electrochemical potential than copper. Alternatively additionally, a copper material portion in a bonding pad may include at least 10% volume fraction of (200) copper grains to provide high volume expansion toward a mating copper material portion. The mating copper material portion may be formed with at least 95% volume fraction of (111) copper grains to provide high surface diffusivity, or may be formed with at least 10% volume fraction of (200) copper grains to provide high volume expansion.

公开(公告)号：US20230127904A1

公开(公告)日：2023-04-27

申请号：US17821659

申请日：2022-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shingo TOTANI ,  Kensuke ISHIKAWA ,  Fumitaka AMANO

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/522

Abstract: A method of forming a semiconductor structure includes forming a semiconductor device over a substrate, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, where the connection-level metal interconnect structure is electrically connected to a node of the semiconductor device and is embedded in the connection-level dielectric layer, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure containing cobalt from a bottom of the via portion of the integrated line-and-via cavity without completely filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that contains copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity on the conductive via structure.

公开(公告)号：US20220336394A1

公开(公告)日：2022-10-20

申请号：US17809991

申请日：2022-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kensuke ISHIKAWA ,  Shingo TOTANI ,  Fumitaka AMANO ,  Rahul SHARANGPANI

IPC: H01L23/00

Abstract: A bonded assembly includes a first semiconductor die that includes first metallic bonding structures embedded within a first bonding-level dielectric layer, and a second semiconductor die that includes second metallic bonding structures embedded within a second bonding-level dielectric layer and bonded to the first metallic bonding structures by metal-to-metal bonding. One of the first metallic bonding structures a pad portion, and a via portion located between the pad portion and the first semiconductor device, the via portion having second tapered sidewalls.