公开(公告)号：US20240321742A1

公开(公告)日：2024-09-26

申请号：US18463752

申请日：2023-09-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Li LI ,  Takashi INOMATA

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a layer contact via structure vertically extending through a subset of the electrically conductive layers and a subset of the insulating layers that includes the bottommost insulating layer, and contacting a surface of a topmost electrically conductive layer within the subset of the electrically conductive layers.

公开(公告)号：US20240321740A1

公开(公告)日：2024-09-26

申请号：US18359697

申请日：2023-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi INOMATA ,  Li LI ,  Masanori OISUGI

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers have different lateral extents that decrease along an upward vertical direction from a bottommost insulating layer to a topmost insulating layer of the insulating layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a layer contact via structure vertically extending through a subset of the electrically conductive layers and a subset of the insulating layers that includes the bottommost insulating layer, contacting a top surface of a topmost electrically conductive layer within the subset of the electrically conductive layers, and having a topmost surface below a horizontal plane including a topmost surface of the alternating stack.

公开(公告)号：US20210090992A1

公开(公告)日：2021-03-25

申请号：US16582262

申请日：2019-09-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Li LI ,  Yuki KASAI ,  Tatsuya HINOUE

IPC: H01L23/522 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. Annular recesses are formed by laterally recessing the sacrificial material layers around each memory opening. A tubular aluminum oxide spacer is formed at a periphery of each annular recess. A tubular silicon oxycarbide spacer is selectively deposited on each of the tubular aluminum oxide spacers. The tubular silicon oxycarbide spacers are converted into tubular silicon oxide spacers by an oxidation process. Tubular charge storage spacers are formed on inner sidewalls of the tubular silicon oxide spacers. A vertical semiconductor channel is formed over a respective vertical stack of tubular charge storage spacer within each memory opening. The sacrificial material layers are removed to form backside recesses. Electrically conductive material are deposited in the backside recesses to form electrically conductive layers.