公开(公告)号：US20240321740A1

公开(公告)日：2024-09-26

申请号：US18359697

申请日：2023-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi INOMATA ,  Li LI ,  Masanori OISUGI

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, where the electrically conductive layers have different lateral extents that decrease along an upward vertical direction from a bottommost insulating layer to a topmost insulating layer of the insulating layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a layer contact via structure vertically extending through a subset of the electrically conductive layers and a subset of the insulating layers that includes the bottommost insulating layer, contacting a top surface of a topmost electrically conductive layer within the subset of the electrically conductive layers, and having a topmost surface below a horizontal plane including a topmost surface of the alternating stack.

公开(公告)号：US20180006049A1

公开(公告)日：2018-01-04

申请号：US15704370

申请日：2017-09-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takashi INOMATA ,  Nobuo HIRONAGA ,  Junichi ARIYOSHI ,  Tadashi NAKAMURA

IPC: H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11556 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

Abstract: A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.

公开(公告)号：US20240321742A1

公开(公告)日：2024-09-26

申请号：US18463752

申请日：2023-09-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Li LI ,  Takashi INOMATA

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a layer contact via structure vertically extending through a subset of the electrically conductive layers and a subset of the insulating layers that includes the bottommost insulating layer, and contacting a surface of a topmost electrically conductive layer within the subset of the electrically conductive layers.

公开(公告)号：US20230232624A1

公开(公告)日：2023-07-20

申请号：US17577533

申请日：2022-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki IWAI ,  Takashi INOMATA ,  Takayuki MAEKURA

IPC: H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1159 ,  H01L27/11597 ,  H01L27/24 ,  H01L25/00

CPC classification number: H01L27/11582 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1159 ,  H01L27/11597 ,  H01L27/249 ,  H01L27/2454 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1441 ,  H01L2924/1444 ,  H01L2924/14511

Abstract: A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first horizontal direction. Each row of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers. Rows of memory opening fill structures are located within the rows of memory openings. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.