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    Temperature based programming in memory
    2.
    发明授权
    Temperature based programming in memory 有权

    公开(公告)号：US10984876B2

    公开(公告)日：2021-04-20

    申请号：US16445367

    申请日：2019-06-19

    Applicant: SanDisk Technologies LLC

    Inventor： Piyush Dak ,  Mohan Dunga ,  Chao Qin ,  Muhammad Masuduzzaman ,  Xiang Yang

    IPC: G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

    Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.

    SYSTEM AND METHOD FOR IN-SITU PROGRAMMING AND READ OPERATION ADJUSTMENTS IN A NON-VOLATILE MEMORY
    9.
    发明申请
    SYSTEM AND METHOD FOR IN-SITU PROGRAMMING AND READ OPERATION ADJUSTMENTS IN A NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20190295669A1

    公开(公告)日：2019-09-26

    申请号：US15928976

    申请日：2018-03-22

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Piyush Dak ,  Wei Zhao ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Mohan Dunga

    IPC: G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

    Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programing operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.

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