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公开(公告)号:US10218384B2
公开(公告)日:2019-02-26
申请号:US15366859
申请日:2016-12-01
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Eran Sharon , Idan Goldenberg , Ishai Ilani , Idan Alrod , Yuri Ryabinin , Yan Dumchin , Mark Fiterman , Ran Zamir
Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.
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公开(公告)号:US09825638B2
公开(公告)日:2017-11-21
申请号:US14198374
申请日:2014-03-05
Applicant: SanDisk Technologies LLC
Inventor: Yan Dumchin , Yair Baram , Michael Tomashev , Leonid Minz , Yevgeny Kaplan , Suzanna Zilberman
CPC classification number: H03L7/07 , G01R31/28 , G01R31/31725 , G06F1/08 , G06F1/206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: A virtual critical path (VCP) circuit is defined separate from an actual critical path circuit. The VCP operates in accordance with a special clock signal. The actual critical path circuit operates in accordance with a system clock signal. The VCP circuit has a signal timing characteristic substantially equal to that of the actual critical path circuit. The VCP circuit includes computational circuitry defined to compute an output value based on an input value, and comparison circuitry defined to compare the output value with an expected result value. A match between the output value computed by the VCP circuit and the expected result value indicates that a frequency of the special clock signal is acceptable. The VCP circuit is used to determine a maximum acceptable frequency of the special clock signal. A frequency of the system clock signal is then set to the maximum acceptable frequency of the special clock signal.
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