公开(公告)号：US20210383886A1

公开(公告)日：2021-12-09

申请号：US16891336

申请日：2020-06-03

Applicant: SanDisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon

IPC: G11C29/42 ,  G11C29/18 ,  G11C29/44

Abstract: Technology for error correcting data stored in memory dies is disclosed. Codewords, which may contain data bits and parity bits, are stored on a memory die. The memory die is bonded to a control die through bond pads that allow communication between the memory die and the control die. The codewords are decoded at the control die based on the parity bits. If the control die successfully decodes a codeword, the control die may send the data bits but not the parity bits to a memory controller. By not sending the parity bits to the memory controller, substantial bandwidth is saved. Also, substantial power may be saved. For example, the interface between the control die and the memory controller could be a high speed interface.

公开(公告)号：US10474525B2

公开(公告)日：2019-11-12

申请号：US14823747

申请日：2015-08-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eran Sharon ,  Ariel Navon ,  Idan Alrod ,  Alexander Bazarsky

IPC: G11C11/56 ,  G06F11/10 ,  G11C16/28 ,  G06F3/06 ,  G11C29/52

Abstract: A data storage device includes a memory, a first module, and a second module. The first module is configured to sense data stored at the memory to generate a first set of soft bits having a first number of bits. The second module is configured to perform an operation using the first set of soft bits to generate a second set of soft bits having a second number of bits that is less than the first number of bits. In an illustrative implementation, the second set of soft bits is used in connection with a three-stage decoding process to decode a set of hard bits that represents the data.

公开(公告)号：US10394649B2

公开(公告)日：2019-08-27

申请号：US15921184

申请日：2018-03-14

Applicant: SanDisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

IPC: G11C29/04 ,  G06F11/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  G11C11/56 ,  G11C16/32

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

公开(公告)号：US20190163367A1

公开(公告)日：2019-05-30

申请号：US16262125

申请日：2019-01-30

Applicant: SanDisk Technologies LLC

Inventor： Alexander Bazarsky ,  Grishma Shah ,  Idan Alrod ,  Eran Sharon

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0411

Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

公开(公告)号：US10236909B2

公开(公告)日：2019-03-19

申请号：US15475666

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  Idan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  Idan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  H03M13/00 ,  G06F3/06

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US10218384B2

公开(公告)日：2019-02-26

申请号：US15366859

申请日：2016-12-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eran Sharon ,  Idan Goldenberg ,  Ishai Ilani ,  Idan Alrod ,  Yuri Ryabinin ,  Yan Dumchin ,  Mark Fiterman ,  Ran Zamir

IPC: G06F11/10 ,  G06F3/06 ,  H03M13/11 ,  H03M13/17 ,  H03M13/37

Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.

公开(公告)号：US10158380B2

公开(公告)日：2018-12-18

申请号：US15371167

申请日：2016-12-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eran Sharon ,  Alexander Bazarsky ,  Idan Goldenberg ,  Stella Achtenberg ,  Omer Fainzilber ,  Ran Zamir

IPC: G11C29/00 ,  H03M13/00 ,  G06F3/06 ,  G06F11/10 ,  H03M13/29

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

公开(公告)号：US10116333B2

公开(公告)日：2018-10-30

申请号：US15223531

申请日：2016-07-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ran Zamir ,  Alexander Bazarsky ,  Stella Achtenberg ,  Omer Fainzilber ,  Eran Sharon

IPC: H03M13/11 ,  G11C16/08 ,  G06F11/10 ,  H03M13/00 ,  G11C16/16 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.

公开(公告)号：US10110249B2

公开(公告)日：2018-10-23

申请号：US15244444

申请日：2016-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xinmiao Zhang ,  Alexander Bazarsky ,  Ran Zamir ,  Eran Sharon ,  Idan Alrod ,  Omer Fainzilber ,  Sanel Alterman

IPC: H03M13/00 ,  H03M13/11 ,  G06F11/10 ,  G11C29/52

Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.

公开(公告)号：US09952944B1

公开(公告)日：2018-04-24

申请号：US15333440

申请日：2016-10-25

Applicant: SanDisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

IPC: G11C16/10 ,  G06F11/16 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C29/52 ,  G11C2207/2281

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.